[time-nuts] Divider pecking order ?

[Bruce Griffiths]

Magnus Danielson wrote:
> Bruce Griffiths wrote:
>> The performance of the sine to square wave conversion clock shaper 
>> circuit may dominate the divider performance.
>> Thus an evaluation of the jitter performance of sine to square wave 
>> conversion circuits would also be informative/useful.
> We should standardise some test for estimating the input contribution.
> I would prefer using various amplitudes, preferably with a measurement 
> of achieved slew-rate.
The input circuit will have an intrinsic jitter plus contributions due 
to the input signal slew rate at the threshold crossing.
A resultant measured performance of the form:
trigger jitter~ SQRT( 1E-22 + (1E-4/S)^2) plus other terms
where the actual numbers depend on the particular input clock shaping 
circuit may be expected.

>> If one is using a digital divider in a narrow band PLL the close in 
>> phase noise performance of the divider may be more important than its 
>> phase noise floor, in which case an ECL or CML divider (or at least a 
>> divider using a CML or ECL resynchronising flipflop) may be a better 
>> choice than a TTL or CMOS divider, especially if a low noise diode 
>> mixer is used as a phase detector is used.
> I have reason to beleive that pulse-width factor has great importance 
> in the produced result for mixer-based measurements. I have not had 
> the time to make any conclusive measurements or theoretical work for 
> it, it just looks like that.
Yes, NIST have shown that the mixer input signal should either be a 
relatively low distortion sinewave or the duty cycle of a square wave 
should be close to 50%.
This may make it difficult to measure the phase noise of those dividers 
with outputs that don't have a 50% duty cycle.
Achieving accurate quadrature between the mixer/phase detector inputs 
can be critical in classical mixer based systems.

Divider jitter will also have contributions due to aliased noise from 
the input signal.
>> Thus characterising divider phase noise may also be useful, although 
>> it may be difficult to do this for divider output frequencies much 
>> below 1Mhz or so.
> Indeed.
>
> It's a pitty that the SIA-3000 stops doing meaningful measurements at 
> 11 MHz... and lower. If someone could tell me how to overcome that, I 
> would be very greatful.
>
The TSC5120A allows phase noise measurements on signals with frequencies 
down to 1MHz.
Classical diode mixer based systems can go somewhat lower in frequency.
> Cheers,
> Magnus
>
For those dividers that have a buffered 10MHz sqare wave output 
measurement of the jitter of lower frequency outputs with respect to the 
buffered 10MHz output may provide a better measure of divider 
performance as the jitter due to the clock conditioning/shaping circuit 
should be largely common mode.

Bruce