[time-nuts] How to detect PLL lock

[Bob Camp]

Hi

A very common approach, that also takes care of a few other issues is to simply declare the upper and lower 10% of the EFC range to be "out of bounds". Any time the PLL gets into those regions declare it to be unlocked. Some people use a lot less than 10%, but then find out that their detector does not quite make it to (say 99%) in all cases. 

The other case you need to worry about with an XOR is total loss of one input. The detector output will go to center scale and just sit there. There is nothing you can do on the output side to catch that condition. You can either detect loss of input directly ( = measure input amplitude) or you can put in a couple of flip flops to figure out when it happens ( = put in a sequential detector).

Bob


On Nov 6, 2010, at 5:48 PM, Roberto Barrios wrote:

> Hello,
> 
> I’ve built a James Miller style GPSD with a Rockwell Jupiter, 74AC86 as phase detector and Isotemp OCXO. Division from 10Mhz to 10kHz is done with a 12F675 PIC that also outputs other frequencies and I also included a 16F88 that gives information as OCXO oven info and various GPS status indicators got from the NMEA string. Everything is built on a PCB similar to the Jupiter GPS. I built the PCB by plotting with a resistive pen directly on the copper with a plotter. It works reasonably well as compared to a Trimble thunderbolt, as per my limited knowledge. Some pictures of the result:
> 
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> 
> 
> 
> I would also like to include PLL lock indication with a LED, but I’m struggling to find a reliable indicator. I’ve tried using the OCXO’s control voltage, which stabilizes when the PLL is locked as an indicator, monitoring it with an ADC of the PIC. Resolution is only around 14mV because of the voltage divider before the ADC input. I can’t make it react as desired to unlocks, I tried some formulas but it is always either too strict or too loose. I’ve also timed the duty cycle of the 74AC68phase detector output with a timer, but I guess the granurality (10Mhz/4) is too coarse to precisely detect when it’s constant. For either reason, the “PLL LOCK” led is lit when it shouldn’t or viceversa.
> 
> Does anyone have a practical, “easily” implementable solution for the lock indicator in this vaguely-nut GPSDO, that this newbie could work out ? Ideally it would be implemented in software, but I understand this modest hardware may have severe limitations.
> 
> Thank you,
> Roberto EB4EQA
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