[time-nuts] How to detect PLL lock

[Roberto Barrios]

Hello,

Thank you Ignacio and all of you, specially those that replied :-)

The convergence idea is the one that I like most, simply because it required 
no additional hardware. I've plotted EFC against time (seconds) in the 
attached file. The bumps after the PLL was locked are caused by GPS a few 
seconds after I deliberately disconnected the antenna.

I like the idea of calculating a convergence value and studying the 
frequency of zero crossings to each side of it. Although with some effort I 
guess I will be able to implement it, I'am not familiar with convergence 
algorithms. Is there somewhere a reasonably (non-)advanced paper about it 
you can point me to?

The other ideas are still very interesting and since I am doing this just as 
a learning exercise, I will eventually experiment all of them.

Again, thank you. What a great list this is.

Roberto EB4EQA


Date: Sun, 07 Nov 2010 14:06:20 +0000
From: "Poul-Henning Kamp" <phk at phk.freebsd.dk>
Subject: Re: [time-nuts] Fw: How to detect PLL lock
To: Discussion of precise time and frequency measurement
<time-nuts at febo.com>
Message-ID: <33479.1289138780 at critter.freebsd.dk>


If you have a microcontroller, isn't it simpler to just look for
convergence in the development of the error term ?

You're probably not in any big hurry for exact convergence anyway,
so overdampen the PLL and simply check that the redidual decreases
towards zero.

Once you have locked the PLL, the fastest way to detect loss of
lock, in particular if you use too high time-constant, is the
too low frequency of zero crossings in the residual.

Poul-Henning


-- 
Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG         | TCP/IP since RFC 956
FreeBSD committer       | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

On Nov 6, 2010, at 5:48 PM, Roberto Barrios wrote:

> Hello,
>
> I?ve built a James Miller style GPSD with a Rockwell Jupiter, 74AC86 as 
> phase detector and Isotemp OCXO. Division from 10Mhz to 10kHz is done with 
> a 12F675 PIC that also outputs other frequencies and I also included a 
> 16F88 that gives information as OCXO oven info and various GPS status 
> indicators got from the NMEA string. Everything is built on a PCB similar 
> to the Jupiter GPS. I built the PCB by plotting with a resistive pen 
> directly on the copper with a plotter. It works reasonably well as 
> compared to a Trimble thunderbolt, as per my limited knowledge. Some 
> pictures of the result:
>
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
> http://www.rbarrios.com/public/_MG_6553.jpg
>
>
>
> I would also like to include PLL lock indication with a LED, but I?m 
> struggling to find a reliable indicator. I?ve tried using the OCXO?s 
> control voltage, which stabilizes when the PLL is locked as an indicator, 
> monitoring it with an ADC of the PIC. Resolution is only around 14mV 
> because of the voltage divider before the ADC input. I can?t make it react 
> as desired to unlocks, I tried some formulas but it is always either too 
> strict or too loose. I?ve also timed the duty cycle of the 74AC68phase 
> detector output with a timer, but I guess the granurality (10Mhz/4) is too 
> coarse to precisely detect when it?s constant. For either reason, the ?PLL 
> LOCK? led is lit when it shouldn?t or viceversa.
>
> Does anyone have a practical, ?easily? implementable solution for the lock 
> indicator in this vaguely-nut GPSDO, that this newbie could work out ? 
> Ideally it would be implemented in software, but I understand this modest 
> hardware may have severe limitations.
>
> Thank you,
> Roberto EB4EQA
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