[time-nuts] Help with TCXO

Azelio Boriani azelio.boriani at screen.it
Tue Dec 6 15:47:24 EST 2011


I have read about the two main delay line techniques: the vernier delay
line and the tapped delay line. These require a sort of on-the-fly
calibration virtually for every sample you get because of the temperature
and power supply dependency of the delay itself. Presently my
time-to-digital converter has a 2.5nS resolution made only by counters,
based on a 100MHz clock and on the capabilities of the Digital Clock
Manager in the Spartan3 XC3S50 FPGA. In your opinion what resolution can I
get from a Spartan3 (without any calibration) using delay lines? I have to
learn how to manage delay lines and how to direct their placement for
time-nut purposes.

On Tue, Dec 6, 2011 at 6:11 PM, Bob Camp <lists at rtty.us> wrote:

> Hi
>
> Actually you can get to sub ns resolution with a delay line in a modern
> cheap FPGA. Weather you can get to sub 50 ps across the full window is open
> to a bit of debate.
>
> The amount of hassle goes up as your resolution gets better. Without heroic
> efforts, sub 200 ps is quite possible.
>
> Bob
>
> -----Original Message-----
> From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
> Behalf Of Azelio Boriani
> Sent: Tuesday, December 06, 2011 10:25 AM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] Help with TCXO
>
> Yes, with an analog interpolator you can. Without an analog interpolator
> and without using the vernier delay line (and other tricks like that), the
> FPGA can only get to nS resolution so far (for example, in a Spartan3 or
> equivalent). To implement a vernier delay line you need also to control the
> logic translator and the technology fitter and know by heart your logic
> chip. Maybe one day they pop up with a time-nut FPGA compiler that is aware
> of intentionally-placed delay lines and stuff like this.
>
> On Tue, Dec 6, 2011 at 3:43 PM, Attila Kinali <attila at kinali.ch> wrote:
>
> > On Tue, 29 Nov 2011 11:23:26 +1100
> > Michael Malloy <mechano at gmail.com> wrote:
> >
> > > let me know if you want schematics for my other designs
> >
> > I'm always interested in learning from others.
> > So, if it would be not too much a hassle, i'd greatly
> > appreciate if you could publish yous schematics/designs.
> > Especially, if you can write a few words on what your
> > design decisions were.
> >
> >                        Attila Kinali
> > --
> > The trouble with you, Shev, is you don't say anything until you've saved
> > up a whole truckload of damned heavy brick arguments and then you dump
> > them all out and never look at the bleeding body mangled beneath the heap
> >                -- Tirin, The Dispossessed, U. Le Guin
> >
> > _______________________________________________
> > time-nuts mailing list -- time-nuts at febo.com
> > To unsubscribe, go to
> > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> > and follow the instructions there.
> >
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>



More information about the time-nuts mailing list