[time-nuts] Frequency multiplication

[Bob Camp]

Hi

The noise depends a *lot* on exactly which part you are talking about. It
also depends on weather you are using the (noisy) internal PLL's or just
talking about the (not quite so noisy) gates. A "good guess" for most FPGA
PLL's is around -110 to -130 dbc at a few hundred KHz offset. 

On top of the basic noise floor, some chips have charge pumps in them that
create very real spurs. Others have internal oscillators related to setup
and operation. In some cases these can be turned off, in others not so much.

Bottom line - there's a lot to look into, and they are unlikely to help you
out. 

Bob

-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Geraldo Lino de Campos
Sent: Wednesday, February 02, 2011 12:23 PM
To: time-nuts at febo.com
Subject: [time-nuts] Frequency multiplication

Following the thread on frequency multiplication, does someone know about
the phase noise of the FPGAs PLLs? I couldn't find information on this.
If phase noise is acceptable, it can be a flexible and economical solution.

-- 
------------------------------------
Geraldo
geraldo at decampos.net
_______________________________________________
time-nuts mailing list -- time-nuts at febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.