[time-nuts] Frequency multiplication

jimlux jimlux at earthlink.net
Sat Feb 5 11:13:56 UTC 2011


On 2/5/11 3:04 AM, Magnus Danielson wrote:
> On 05/02/11 04:33, jimlux wrote:
>> On 2/4/11 1:18 PM, Magnus Danielson wrote:
>>> On 02/02/11 19:47, Hal Murray wrote:
>>>>
>>>>> Bottom line - there's a lot to look into, and they are unlikely to
>>>>> help you
>>>>> out.
>>>>
>>>> There are a lot of FPGAs used in DSP applications where the clock to
>>>> the
>>>> front end ADC is critical. So I'd expect there would be some in-house
>>>> knowledge about this area. It may be that all the help you will get is
>>>> "Don't do that."
>>>
>>> You don't feed the ADC from the FPGA if you can avoid it.
>>>
>>
>>
>> especially if your ADC clock is a different frequency from the processor
>> clock that's being used for most of the other logic on the FPGA. I'd
>> give a ballpark estimate of 20-30 dB isolation between the two on a
>> Virtex 2.
>
> If you do it naively. You can do better, but it is not worth the time in
> most cases.
>
> FPGAs is a lovely sea of logic. The
> MGT/GTP/whatever-high-speed-I/O-is-called-this-week has much better
> timing. FPGAs are perfect for taking care of the data and processing.
> Just do the timing sufficiently isolated from the FPGA. Once size
> doesn't fit all. FPGAs is there to fit the need of relative high speed
> and relative high integration of logic.

And where in-situ changes in the signal processing are needed (e.g. in a 
software defined radio), the reprogrammable FPGA is a good fit.   But 
there is a tradeoff.. you might want to give the downstream 
users/programmers the ability to change sample rates, prompting the idea 
of driving the data converter from the FPGA, without needing to add 
external components to provide that function.


It has taken more and more of
> the full custom market, but will not take the full ASIC or full-custom
> market.
>




More information about the Time-nuts_lists.febo.com mailing list