[time-nuts] Frequency multiplication

[jimlux]

On 2/5/11 3:54 AM, Magnus Danielson wrote:
> On 05/02/11 12:13, jimlux wrote:
>> And where in-situ changes in the signal processing are needed (e.g. in a
>> software defined radio), the reprogrammable FPGA is a good fit. But
>> there is a tradeoff.. you might want to give the downstream
>> users/programmers the ability to change sample rates, prompting the idea
>> of driving the data converter from the FPGA, without needing to add
>> external components to provide that function.
>
> The FPGA can be a part of that solution, with DDSes, programmable
> dividers etc, but the actual clock should preferably not go through the
> FPGA before hitting ADCs and DACs.
>
I agree, but if you want the clock rate to be changeable/selectable, 
driven arbitrarily by logic in the FPGA, you're kind of stuck.

A typical scenario (which could be fixed by minimal external circuitry) 
is turning the clock entirely off to save power in the DAC/ADC.  Or 
where you want to run the converters at a lower rate to save power when 
processing a narrower band signal.

  In the software radio area, we usually have at least two clocks in the 
system.. a CPU clock running at something like 66 or 75MHz (or something 
convenient) and a reference oscillator (used for generating the local 
oscillators, etc., as well as the sampling clocks) at 50-100 MHz, 
although the sampling might be divided down some from that.  The CPU 
clock is generally of lower quality (e.g. not a TCXO, not necessarily 
good phase noise) and the reference oscillator is usually fairly good 
(TCXO or OCXO, good phase noise since it's being multiplied up to 
microwave frequencies, etc.)

A low parts count approach to meeting the overall need might be to have 
a very small "clock FPGA" that is clocked ONLY by the external clock and 
generates the needed DAC and ADC clocks, with whatever dividing, etc. 
At least then, you don't have to deal with isolation from the CPU bus clock.

That would be an alternative to adding a lot of external clock mux 
logic, with dividers and such.  You might even be able to use a suitable 
onetime programmable FPGA in a small package to implement a "generic 
clock source" with enough sophistication, but still with minimal 
degradation.