[time-nuts] power spectrum of hard limiter output

[ehydra]

The classical approach is to heavily band-limit the input of an 
following hard-limiter. But would it possible to merge both functions in 
several stages of an IF-strip?

I think most individuals cannot follow much of this idea but time-nuts 
have the same problem :-)

My main interest is a practical (reduced to standard parts to buy) CMOS 
inverter IF-strip where the individual stages are ac-coupled.
So it is possible to integrate a high-pass filter via the coupling 
capacitor and low-pass via the cross connected capacitor over the 
inverters. I think the interstage capacitor also removes 1/f noise of 
the signal from the individual pre-stage inverter. CMOS having more 1/f 
noise than bipolar transistors under approx. 1 KHz but can be 
comfortable from 100 KHz to 1 MHz. The nice thing with CMOS is cheapness 
and simplicity.

So the questions are:
1. maximum useful amplification
2. depends on noise in first stage
3. compression on MOSFET inverter gives spectral regrowth
4. limiting of burst noise in rf signals
5. trying to avoid any form of automatic gain control
6. etc.

I played with SPICE models in LTspice and practical with SpectrumLab 
using CD4007 inverters as IF-strip at 25 KHz.

I try to be practical and avoid heavy mathematicals.

It works fine if one think of the price of such simple parts! But I'm a 
little over my edge how to optimize it further.

Any suggestions are welcome. I don't have access to IEEE papers.

This paper is interesting because it mentions main aspects but looses 
itself in CDMA specific aspects:
www4.ncsu.edu/~kggard/kg_papers/MTT_05_FrontEnd_Distortion.pdf

regards -
Henry

(Sorry for bad english)