[time-nuts] 50:50 duty from a PRS10

[David C. Partridge]

>> Hello,
>>
>> I have a PRS10 rubidium which gives a 1pps output. The output is a 10 
>> us positive pulse.
>>
>> I need to convert that to a 50:50 duty cycle pulse. Still 1pps.
>>
>> I'm hoping for a simple circuit rather than having to use a pic.
>>
>> I don't mind a bit of propagation delay, but I need to preserve the 
>> low jitter on the rising edge, and hopefully also the falling edge.
>>
>> Any ideas out there
>>
>> Regards
>>
>> Steve

Feed the PPS into both inputs of a 74HC164 clock with 10MHz to clock, ~CLR grounded. Take outputs C and H into J-K Flip-Flop (74HC112) also clocked with 10MHz - I think that will do it.

See the schematic of my Frequency Divider <http://perdrix.co.uk/FrequencyDivider/Frequency%20Divider%202%20Schematic.pdf> where I take the RCO output from an AC163 and use this to derive 1MHz 50% duty cycle.  The full write up is here: <http://perdrix.co.uk/FrequencyDivider/index.html>

Regards,
David Partridge
-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On Behalf Of Magnus Danielson
Sent: 22 July 2011 10:02
To: time-nuts at febo.com
Subject: Re: [time-nuts] 50:50 duty from a PRS10

On 07/22/2011 05:38 AM, Dave M wrote:
>
>> Hello,
>>
>> I have a PRS10 rubidium which gives a 1pps output. The output is a 10 
>> us positive pulse.
>>
>> I need to convert that to a 50:50 duty cycle pulse. Still 1pps.
>>
>> I'm hoping for a simple circuit rather than having to use a pic.
>>
>> I don't mind a bit of propagation delay, but I need to preserve the 
>> low jitter on the rising edge, and hopefully also the falling edge.
>>
>> Any ideas out there
>>
>> Regards
>>
>> Steve
>
>
> The simplest way that I can think of is to feed both inputs of an XOR 
> gate with your 1pps signal to double it to 2pps, then feed the XOR 
> output into a flipflop to get back to 1pps with 50% duty cycle. You 
> might have to delay the 1pps into one of the XOR inputs with a small 
> RC to reliably trigger the flipflop. Use 74HC or AC gates and the 
> jitter should be tolerable.

The rise and fall transitions which trigger the XOR gate will cause the XOR output to occur at those times and not with a 500 ms spread as you wish them to be.

You really need some form of memory that recalls that we have a "high" 
period for 500 ms rather than the 10 us. The method (and inherent
precision) will vary, but there is no alternative to this memory. 
Dividers from the 10 MHz ensures it is a synchronous timed transition. 
If the fall transition isn't critical, the 555 solution or similar will do.

Cheers,
Magnus

_______________________________________________
time-nuts mailing list -- time-nuts at febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.