[time-nuts] time interval with 10 ps resolution using cheap FPGA ?

[Tijd Dingen]

Oh yeah, forgot to mention this with regard to the tapped delay line...

Make sure you don't use the fpga dcm/pll for clock generation. It is
too jittery. Generate an external reference as high as feasible that
is still acceptable to the IOB's of the fpga you intend to use. It makes
sense to make it an integer multiple of a clean 10 MHz reference clock.

That way you have a clean clock that you can use for two things:
- reference counter
- sampling the delay line taps

The reason you want low jitter for these parts of the design is that it
directly affects the timing uncertainty of your measurements.

After that you will probably want to use a lower clock for the rest of
the data path to give you some more relaxed timings to work with.

regards,
Fred