[time-nuts] 50/60 Hz clocks

[WB6BNQ]

Paul,

Even the low end regular DDS, like the 9831, using a 10 MHz striaght through clock
will produce a frequency of   60.0004568696022  Hz or   50.0003807246685  Hz as an
output.  Simple (ok, perhaps not) amplification after that will get the clock
drive needed.  Just because some of Analog Devices' more unique products sound
neet, they do not always perform as well as the simpler parts.

While not easy to find, here is a tool on the A/D site that allows for design
simulation of the DDS clock functions.  You can even see a tabular table of the
spur generation.  In the above simulation case they are quite low.

http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx


Bill....WB6BNQ


paul swed wrote:

> Speaking of dds the ad5932 can do this also 10 MC in and 60.20069122 out
> Change 1 bit and you get 59.6046448 it would be quite easy to bounce back
> and fourth between the two frequencies like the power company does over
> time. Thats a small 16 pin chip for a few $. Plus a small pic to make it do
> what you might want.
> It could also use any number of other ref clock frequencies1, 5, 15, 20, 50
> MC and even ones that aren't sensible to drive the chip.
> You can take the square wave out or a true sine wave or a triangle if
> needed.
> Regards
> Paul
> WB8TSL
>
> On Sun, Mar 20, 2011 at 7:22 PM, Magnus Danielson <
> magnus at rubidium.dyndns.org> wrote:
>
> > On 03/21/2011 12:10 AM, Hal Murray wrote:
> >
> >>
> >>  If the plan is to drive a mechanical clock, I assume long term stability
> >>> is
> >>> more important than phase noise. Many small microcontrollers (I use
> >>> 8051's
> >>> from Silabs) have a built-in PLL that can be set to run at 15 MHz from an
> >>> external 10 MHz reference (applied to the external oscillator input), and
> >>> use the program space to implement a divider that will give you exactly
> >>> 60
> >>> Hz. That is a one chip solution. The processor will accept the sinewave
> >>> from
> >>> the reference oscillator without extra shaping circuit.
> >>>
> >>
> >> In case your favorite chip doesn't have a PLL...  You can run directly
> >> from a
> >> 10 MHz clock as long as you can tolerate a bit more phase noise and/or
> >> spurs.
> >>  The software just gets a bit more complicated.  Instead of dividing by N,
> >> it
> >> has to mix delays of N and N+1 in the right ratio.
> >>
> >> You can also do it with a DDS in a FPGA.  The trick is to use a decimal
> >> adder
> >> rather than a binary adder.  60/10000000 in binary isn't a clean fraction
> >> so
> >> the clock will drift slightly.
> >>
> >>
> >> [This should be simple, but I'm not sure I've got it right.]
> >>
> >> On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30
> >> or
> >> 16*1E9*1E9 or 16E18.  Call it 1E19.  We are clocking at 10E7 Hz, so (worst
> >> case) the counter will be off by a full cycle every 1E12 seconds.
> >>
> >> There are 3E9 seconds per century.  So after a century, the clock would be
> >> off by 3E-3 cycles or 50 microseconds.
> >>
> >
> > On the other hand, it would not be difficult to make a DDS which hit
> > 60/10000000 exactly. Reducing it by 20 on each side you get 3/500000 so a 19
> > bit accumulator (mod 500000) incrementing with 3 on every 100 ns period
> > would do it. A LUT for sine would be possible. Playing a few tricks with the
> > LUT table (realizing that the LUT would be walked through three times with
> > three different start-alignments) converts it into a LUT of the same size
> > and a increment by one or decrement by one counter modulus 500000. A
> > decrement by one counter allows wrap-around loading with 499999 easy. CPLD
> > or CMOS/TTL implementations would be trivial for the counter. The LUT will
> > be large...
> >
> > Cheers,
> > Magnus
> >
> >
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