[time-nuts] 50/60 Hz clocks

[Magnus Danielson]

On 03/22/2011 11:45 PM, Hal Murray wrote:
>
> magnus at rubidium.dyndns.org said:
>> On the other hand, it would not be difficult to make a DDS which hit  60/
>> 10000000 exactly. Reducing it by 20 on each side you get 3/500000 so  a 19
>> bit accumulator (mod 500000) incrementing with 3 on every 100 ns  period
>> would do it.
>
> Neat.  Thanks.
>
> I'd noticed that adding in decimal rather than binary would make exact target
> frequencies in some cases, but I hadn't generalized to adding modulo N.
> Using N of 10,000,000 with a 10 MHz clock gets you all exact integer
> frequencies in the audio range.

Which was my main point... it doesn't have to be THAT complex. A 500000 
entry LUT is however expensive.

>> A LUT for sine would be possible. Playing a few  tricks with the LUT table
>> (realizing that the LUT would be walked  through three times with three
>> different start-alignments) converts it  into a LUT of the same size and a
>> increment by one or decrement by one  counter modulus 500000. A decrement by
>> one counter allows wrap-around  loading with 499999 easy. CPLD or CMOS/TTL
>> implementations would be  trivial for the counter. The LUT will be large...
>
> More neat.  Thanks again.  It's just a simple state machine cycling through
> some collection of states.

Exactly. It really helps when trying to understand spurious response. A 
DDS has a large number of states and for most frequencies, all states 
will be visited before looping. A 32-bit DDS clocked at 10 MHz wraps in 
429.4967296 s. Half the possible settings will wrap quicker (at various 
power of 2 variants).

> If we are willing to rearrange the LUT/ROM, we can simplify the next state
> calculation from a modulo adder to a re-loadable counter.

Which is what I propose above.

Cheers,
Magnus