[time-nuts] multi input counter

Magnus Danielson magnus at rubidium.dyndns.org
Thu Oct 6 19:24:57 EDT 2011

Hi Jim,

On 07/10/11 01:02, Jim Lux wrote:
> since I rudely tagged onto someone else's search for a suitable counter,
> I'll restate my need here..
> I want to set up an experiment to characterize a bunch (several dozen?)
> of cheap XOs (e.g. SiTime parts) over temperature and time and power
> cycles. I'm not looking for 1e-15 adev at 100 seconds kind
> of performance: maybe more like 1E-6 or 1E-7 ADEV at 100-1000 seconds
> (i.e. does the frequency of a 10MHz oscillator vary more than 1 Hz over
> 20 minutes?)

That is what you are going to measure :)

> Something like a programmable MUX into one counter would work, but if
> you have 20 odd oscillators, making ADEV measurements for tau of 1-10
> seconds on all of them would be tough.


> If I were doing it in an FPGA, I'd just setup a bunch of counters and
> latch them once a second, then shoot the counts out a serial port in
> some fashion (might still wind up doing that). Or, one could latch a
> single common counter with each of the unknowns divided down by, say,
> 10million. I think the two measurements are basically equivalent (one is
> measuring period, the other frequency, essentially).
> Or, any of a variety of microcontrollers can do it.
> Or, a combination of microcontroller + FPGA.
> I think what I was hoping is that there's some already existing box that
> someone sells (or sold in the past) that does this. If not, I'll just
> build something. Probably the FPGA approach.. it seems simplest.. any
> suggestions from the assembled multitude for a inexpensive eval board
> that has an FPGA with suitable input pins for the output from those
> SiTime oscillators (and any other grungy oscillators I scrounge up)?
> Something with, say, 32 inputs/pins brought out to a header on the eval
> board would be nice. maybe the Spartan 3A or 3E for $200? (I'll have to
> look at the data sheets)
> or, given that I'm not looking for ultimate performance, are there any
> particular FPGAs to stay away from that are notoriously bad in this kind
> of timing application.

You would be able to use the standard 3E development-board for sure.

If you run your 10 MHz into the clock input, you could run a 
time-stamper clock with it and then use a suitable divide down counters 
for each time-stamped clock.

Consider that you have 7 digits of time-stamp value and 8 digits of hex 
code for time-stamped inputs and a carrige return, you need to output 16 
bytes. Considering that it takes 32 read-outs a second in peak. This 
means 512 bytes a second or a rate of 5120 baud needed, so 9600 baud 
output will do just fine. The time-stamper clock can count in BCD to 
make conversion cheap (and easy to code, just slab 0010 on top of 
digits). A 64 bit wide FIFO is needed to store time-stamps, as they can 
come at high burst rate but low average flow.

It's doable and not too much work to cook up. I did something similar 
before, but I just can't find the code lying around. Sad, since it had 
the serial transmitt code and FIFO stuff more or less what we need.

Oh... look! No CPU!


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