[time-nuts] SLIP vs Ethernet for NTP

Tijd Dingen tijddingen at yahoo.com
Sun Oct 23 13:02:36 EDT 2011



Jim Lux wrote:
> if you're talking asynchronous RS232 (the by far most common, these days)
> off hand, I'd expect the jitter to be on the order of 1/8 bit time, uniformly distributed.  An awful lot of UART implementations generate a 8x clock to sample the input and find the rising edge of
> the start bit.

Funny you should mention that. I was just thinking about what the main contribution to RS232 jitter would be. For fpga purposes I've seen a lot of verilog/vhdl code that does precisely what you descibe. Use a clock that's 8 times the bit clock, which is useful for oversampling the RX. Funny that UART implementations do the exact same thing.

regards,
Fred


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