[time-nuts] 8560E DC Coupling phase noise measurements

John Miles jmiles at pop.net
Tue Oct 25 16:55:06 EDT 2011

> -----Original Message-----
> From: time-nuts-bounces at febo.com [mailto:time-nuts-
> bounces at febo.com] On Behalf Of Loïc MOREAU
> Sent: Tuesday, October 25, 2011 1:01 PM
> To: time-nuts at febo.com
> Subject: [time-nuts] 8560E DC Coupling phase noise measurements
> Hi,
> In the process of measuring phase noise with a 'demphano' gear,  I am a
> reluctant to connect  my 8560E in DC mode to get 30 Hz low frequency
> sensitivity:  the SA input is very sensitive to DC voltage and may  be
> destroyed by a voltage larger than 200mV.
>  So with a LNA having no blocking DC output I would like to know the best
> way to protect the SA.
> I suppose that putting a 100µF capacitor between LNA and SA is not
> especially a good idea as a charged capacitor to DC rail may have the same
> effect that no caps at all.
> I am looking for some advice in that domain to pursue phase noise
> measurements,  for now I connect the SA with a caution after PLL lock and
> measuring the SA input with a DC voltmeter before switching to DC SA input
> but this mode of operation is a bit frightening.
> Any idea ?

The 200 mV limit is only with 0 dB of RF attenuation.  With a quadrature PLL
and LNA, you don't need to use 0 dB.  20 dB is probably OK, and if not, you
can make up for it with more gain.

A pair of back-to-back Schottky diodes would be another alternative. 

-- john

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