[time-nuts] Question about precise frequency / phase measurement
EWKehren at aol.com
EWKehren at aol.com
Fri Apr 20 16:01:56 UTC 2012
Ed
at one time I used two 9 GHz multiplier chains out of FTS 4000's mixed
them, if you are interested contact me off list I may still have them. Have
thrown out many things because I am downsizing in preparation for a move.
Bert
In a message dated 4/20/2012 11:37:16 A.M. Eastern Daylight Time,
eb at telight.com writes:
You may want to look at how that was done many years ago with
frequency difference multiplication as in the old Tracor meters - I
think the 528 was the main one. They synthesized a 9 MHz reference
from one input, and then subtracted it from the other to get a 1 MHz
result, which was used as a reference for another 10 MHz PL
oscillator. The 9 MHz was subtracted from this, and so on to a next
identical stage. The net result is that each stage of this process
multiplies the frequency difference by ten times. These can be
cascaded until you reach the limit of the noise performance of the
stage designs - they managed around 10,000 times fairly readily. This
method can be duplicated fairly easily with modern logic parts. With
a setup like this you can produce a 1 or 10 MHz carrier that can be
counted to very high resolution at one second gating - you just
ignore the carrier digits and look at the multiplied difference
frequency digits. Or, you can subtract the carrier and get just the
multiplied difference - but you have to keep track of the phase info
to know if it's plus or minus.
It's of course possible to use whatever frequencies and stage
multiplication factors you want, but the tradeoffs are in making the
numbers come out rationally (especially if you want a number of
decade multiplier ranges), and the precision and quality of the
intermediate frequency filtering and processing. About ten to one
hundred times per stage is within reason. For example, I have an
experimental (way unfinished) setup started with three stages of 1
GHz PLOs for multiplication, and a 990 MHz reference. This will give
100X per stage, reaching 10E6 difference frequency multiplication at
one second gating, presuming I can manage the phase noise
sufficiently. A quick two-stage setup indicated no problem reaching
10E4, but that last 100X will be tricky - I have to build it up for
real first, with extremely clean power supplies, shielded signal
processing modules, and solid signal routing, just to see if it's
possible. I would not recommend this approach - I'm only doing it
because I happened to have all the main parts on hand. It would be
better to keep everything down to 100 MHz or less for processing in
ECL or ACMOS, and using crystal VCOs and filters.
Ed
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