[time-nuts] PICTIC II ready-made?

[David]

On Fri, 27 Apr 2012 22:13:55 +0200, Azelio Boriani
<azelio.boriani at screen.it> wrote:

>By "preload" I think you mean the configuration step of the logic. It seems
>that the Xilinx one stops the clock after the configuration is done. Anyway
>using small EEPROM based CPLDs you have no clock at all: there is no
>configuration to load.

Wouldn't that also apply to an EEPROM based FPGA?  I have been
thinking that SRAM based devices may be a better match in cases where
you only want to have to program one device.