[time-nuts] Wilkinson TDC

[Bruce Griffiths]

The essentials of a Wikinson TDC can be simplified to the attached 
circuit which only requires the addition of a zero crossing comparator 
to monitor the voltage across the capacitor C1.

A few refinements to improve the capacitor charging current switching 
transitions and the addition of an upper voltage clamp together with the 
use of faster transistors may be useful.

Apart from level shifting to drive the npn and pnp longtailed pairs only 
a 2 bit shift register is required for the synchronisers reducing the 
number of external (to an FPGA or CPLD) logic packages required.
The jitter of the count logic etc., isn't critical and can be 
implemented in an FPGA or CPLD.

With a 100MHz synchroniser and counter clock a resolution of 10ps can be 
achieved with a 1000:1 ratio between charge and discharge currents.

Bruce
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