[time-nuts] Wilkinson TDC

paul swed paulswedb at gmail.com
Sun Apr 29 14:20:09 UTC 2012


Do you have an actual circuit?
It looks a lot like the  old hp5360 counter interpolator.
Regards
Paul

On Sun, Apr 29, 2012 at 3:51 AM, Bruce Griffiths <bruce.griffiths at xtra.co.nz
> wrote:

> The essentials of a Wikinson TDC can be simplified to the attached circuit
> which only requires the addition of a zero crossing comparator to monitor
> the voltage across the capacitor C1.
>
> A few refinements to improve the capacitor charging current switching
> transitions and the addition of an upper voltage clamp together with the
> use of faster transistors may be useful.
>
> Apart from level shifting to drive the npn and pnp longtailed pairs only a
> 2 bit shift register is required for the synchronisers reducing the number
> of external (to an FPGA or CPLD) logic packages required.
> The jitter of the count logic etc., isn't critical and can be implemented
> in an FPGA or CPLD.
>
> With a 100MHz synchroniser and counter clock a resolution of 10ps can be
> achieved with a 1000:1 ratio between charge and discharge currents.
>
> Bruce
>
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