[time-nuts] Wilkinson TDC

[Bruce Griffiths]

David wrote:
> On Mon, 30 Apr 2012 06:51:37 +1200, Bruce Griffiths
> <bruce.griffiths at xtra.co.nz>  wrote:
>
>    
>> The circuit for the Tek 2440 is in the manual.
>> However, it isnt that well executed.
>>      
> I like using the 2440 as an example because the design and theory are
> readily available online.  Its execution only had to be good enough
> for 40ps equivalent time sampling and less than 50 measurements per
> second.  Unfortunately the self calibration logic is obfuscated inside
> of a Tektronix black box custom ASIC.
>
>    

Self calibration should be fairly straightforward:
Just adjust the discharge current source so that the change in count 
associated with a pair of known inputs assumes the design value.
Non linearity calibration is also fairly simple using a statistical fill 
the buckets test with a noisy asynchronous oscillator as the trigger source.


>> Relying on the overload recovery of an unclamped jfet input opamp limits
>> the recovery time and performance as does the unisolated input
>> capacitance of the opamps used to control the current source transistor
>> emitter currents, the Wavecrest interpolators which incorporate several
>> refinements to improve the transient response of the current sources are
>> far better in this respect.
>>      
> By unclamped JFET input opamps do you mean U590B and U590C which are
> used to adjust the ramp start to zero volts and operate open loop
> during the measurement?  With such a slow measurement rate, that
> feedback loop has at least 20ms to complete settling.  I notice that
> they attenuated the open loop gain by a factor of 6.  I wonder if that
> was to lower the noise or to add phase margin to the control loop.
>
>    
One has to establish that the recovery time is indeed sufficiently fast.
This parameter is rarely specified by the manufacturer.
Opamp recovery from saturation can be very slow in some cases as 
parasitic devices may turn on during saturation.
Its generally better to avoid saturation altogether by judicious use of 
feedback (diode) clamping techniques.
Sometimes this may require than an additional opamp be employed in the 
reset circuit.

The attenuation also serves to limit the amount of correction signal 
available during the open loop phase.
Adding opamp  input capacitance at the current source transistor emitter 
nodes does little for transient response and stability.


>> The Wavecrest interpolators also have sub picosecond resolution although
>> their noise is around 3-6ps.
>>      
> Is there a published schematic and theory for the Wavecrest other than
> the patent?  The best information I have found through Google is from
> your own posts here.
>
>    

Not that I'm aware of the relevant patents are fairly detailed.
I gleaned all that I know about it from the patent and associated 
schematics.
Critical damping of the reset circuit is employed to reduce the settling 
time and the use of open loop amplifiers at any phase of the measurement 
cycle is avoided.
The addition of small value resistors in series with the emitters of the 
TAC current switches is also useful in improving their transient response.

>> Bruce
>>
>> paul swed wrote:
>>      
>>> Do you have an actual circuit?
>>> It looks a lot like the  old hp5360 counter interpolator.
>>> Regards
>>> Paul
>>>
>>> On Sun, Apr 29, 2012 at 3:51 AM, Bruce Griffiths<bruce.griffiths at xtra.co.nz
>>>
>>>        
>>>> wrote:
>>>>
>>>>          
>>>
>>>        
>>>> The essentials of a Wikinson TDC can be simplified to the attached circuit
>>>> which only requires the addition of a zero crossing comparator to monitor
>>>> the voltage across the capacitor C1.
>>>>
>>>> A few refinements to improve the capacitor charging current switching
>>>> transitions and the addition of an upper voltage clamp together with the
>>>> use of faster transistors may be useful.
>>>>
>>>> Apart from level shifting to drive the npn and pnp longtailed pairs only a
>>>> 2 bit shift register is required for the synchronisers reducing the number
>>>> of external (to an FPGA or CPLD) logic packages required.
>>>> The jitter of the count logic etc., isn't critical and can be implemented
>>>> in an FPGA or CPLD.
>>>>
>>>> With a 100MHz synchroniser and counter clock a resolution of 10ps can be
>>>> achieved with a 1000:1 ratio between charge and discharge currents.
>>>>          
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