[time-nuts] Understanding Oliver Collins Paper "Design of Low Jitter Hard Limiters"

David davidwhess at gmail.com
Wed Aug 22 08:54:22 EDT 2012


Do you mean with a 7404 hex inverter?  I actually did something like
this recently while adding a 75ns pre-trigger pulse to an existing
fast rise pulse generator.

The pre-trigger pulse ended up having significant pattern dependant
jitter caused by the adjacent TTL divider chain modulating the supply
voltage and the poor power supply rejection of the 7404.  I was easily
able to see the jitter on my 7T11 sampling oscilloscope but on my 2440
(20 GS/sec equivalent time sampling), it was barely perceptible if
that despite ideal conditions.  The peak to peak jitter was about
100ps.

As far as I could tell from the available online documentation, the
TDS220 and TDS3012 have relatively low sample rates and do not support
equivalent time sampling so I would expect them to show even less than
my 2440.

On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani
<azelio.boriani at screen.it> wrote:

>In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see
>the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I
>need the Wavecrest SIA3000?
>
>On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp <lists at rtty.us> wrote:
>
>> Hi
>>
>> Since the Collins approach "tunes" the system for a single frequency input
>> (more or less), the approach is probably not the best for a "many decades"
>> sort of frequency range. There are a number of things that he alludes to in
>> the paper, but does not directly address. The most obvious is the
>> temperature dependance of the "stuff" the system is made of. Another is the
>> simple fact that a non-clipping linear amplifier is likely the best choice
>> for a first stage, provide the input is not already near clipping.
>>
>> Bob
>>
>> On Aug 21, 2012, at 12:50 PM, raj_sodhi at agilent.com wrote:
>>
>> > Hello everyone,
>> >
>> > I am new to this forum.
>> > It looks like a lively discussion on various topics.
>> >
>> > A colleague of mine here at Agilent pointed me to this paper entitled
>> "The Design of Low Jitter Hard Limiters" by Oliver Collins. In Bruce
>> Griffiths' precision time in frequency webpage, this paper is described as
>> "seminal."
>> > (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html)
>> >
>> > Since I'm trying to create a limiter that will accept frequencies
>> ranging from 1 MHz to 100 MHz, I thought it would be good to understand the
>> conclusions of this paper (if not the mathematics as well).  The
>> mathematics turned out to be quite challenging to decode. Has someone on
>> this forum unraveled the equations? It appears Collins has recommendations
>> on the bandwidth and gain of a jitter minimizing limiter, and then extends
>> this analysis to provide the bandwidth and gain of a cascade of limiters.
>>  But the application is still fuzzy.  In figure 5, he shows a graph showing
>> the dependence of jitter on crossing time.  Is the crossing time (implied
>> by equations 7) considered a design parameter one can vary? Also, on figure
>> 4, the "k" parameter has been varied to show the rising waveform as a
>> function of "k".  The threshold is always assumed to be 0.5.  So could "k"
>> be related to "tau", the time constant of the RC filter?
>> >
>> > Thanks in advance for all your help.
>> >
>> > Yours
>> >
>> > Raj
>> >
>> >
>> >
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