[time-nuts] Understanding Oliver Collins Paper "Design of Low Jitter Hard Limiters"

raj_sodhi at agilent.com raj_sodhi at agilent.com
Wed Aug 22 12:09:39 EDT 2012


Hello Everyone,

Thanks to Azelio, Bob and David for their comments.  Special thanks to Magnus for clarifying the intent of this paper. I think I begin to understand the 'k' term.

When I look at jitter, I actually look at residual phase noise using the E5500 phase noise measurement system. One could use a sampling oscilloscope with a clean trigger to do something similar, but for what we do here, customers want to know phase noise spectral density versus frequency.  I have found the region between 1 Hz and 100 Hz offsets to be particularly challenging. Jason Breitbarth, CEO of Holtzworth, wrote a nice paper for microwave Journal on residual phase noise.  
http://www.holzworth.com/Aux_docs/PhaseNoise_Article_MWJ_Jun08.pdf

I have thought more critically about my block diagram, and fortunately, I'm not trying to square up sine waves from 1 MHz to 100 MHz.  These are generated using ECL counters and re-clocking. Just yesterday, I proved to myself that this was working correctly. But there is a situation where I submit a 100 MHz sine wave to this limiter, which then serves as the reference for a phase lock loop. The residual noise of the loop is much higher when the LO is a sine wave as compared to when driven by a square wave.  This is straightforward to visualize. A zero crossing detector will be much more sensitive to noise when the input is a shallow sloped sine wave as compared to a sharp edged square wave.  Perhaps I just need to tinker with the limiter, checking supply noise suppression, thermal noise, etc.

Magnus makes a very good point that the paper only considers a simplified model using white noise as the input. Perhaps once the mathematics have been understood, one could extend the analysis to include 1/f noise at 10 Hz and 100 Hz. But even with white noise input, the mathematics seem crazy hard.  I asked around a couple of folks around here, and the typical response was "has been too many years since I looked at this type of math."  So this could be a good way for me to refresh.

In figures 2 and 3, Collins presents the basic model. An input signal rises from 0 V to V V between times 0 and T. The input slope 'rho_in' is V/T.  Going through an amplifier of gain G, the output waveform is sharper, transitioning from 0 V to V V between times 0 and T/G.  The output slope during the transition period could be related as rho_out (output slope) = g (slope gain) * rho_in (input slope). Dividing the basic voltage gain equation Vout = G * Vin by time, can we reasonably say that voltage gain G is the same as slope gain g?

Assuming white noise at the input of variance No, the autocorrelation function is Rxx(tau) = No*delta(tau). Submitting the amplified random signal through a simple RC low pass filter, we obtain the result of equation 2. In the development of equation 3, the author states that the noise input is not applied for all time.  Rather, it is turned on at time 0 and turned off at time T/G. So equation 3a is a reasonable modification of equation 2; rather than integrate from zero to infinity, integrate from zero to 'th', the threshold crossing time. But equation 3b has me spinning my wheels.  For th > T/G, noise deposited to the capacitor in the filter is now dissipating? But we do not consider noise added once the limiter has saturated, or do we?

Yours

Raj



-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On Behalf Of Azelio Boriani
Sent: Wednesday, August 22, 2012 6:44 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Understanding Oliver Collins Paper "Design of Low Jitter Hard Limiters"

According to

http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf

the real time sampling scope (like the TDS220 or TDS3012) can measure cycle to cycle jitter directly, whereas the equivalent time sampling has only one sample each trigger and a little delay on the sampling point for the next trigger. The displayed waveform is a sort of "sum" of more than one cycle and now I can't figure out what type of picture this can give. The TDS3012 has also the advantage of the Digital Phosphor behavior that can be useful for the jitter analysis. Maybe a stable timebase and low jitter external trigger input are essential. Unfortunately the TDS3012 has a 200ppm timebase...

On Wed, Aug 22, 2012 at 2:54 PM, David <davidwhess at gmail.com> wrote:

> Do you mean with a 7404 hex inverter?  I actually did something like 
> this recently while adding a 75ns pre-trigger pulse to an existing 
> fast rise pulse generator.
>
> The pre-trigger pulse ended up having significant pattern dependant 
> jitter caused by the adjacent TTL divider chain modulating the supply 
> voltage and the poor power supply rejection of the 7404.  I was easily 
> able to see the jitter on my 7T11 sampling oscilloscope but on my 2440
> (20 GS/sec equivalent time sampling), it was barely perceptible if 
> that despite ideal conditions.  The peak to peak jitter was about 
> 100ps.
>
> As far as I could tell from the available online documentation, the
> TDS220 and TDS3012 have relatively low sample rates and do not support 
> equivalent time sampling so I would expect them to show even less than 
> my 2440.
>
> On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani 
> <azelio.boriani at screen.it> wrote:
>
> >In your opinion, if I build a 7404 ZCD and a hard limiter one, can I 
> >see the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) 
> >or do I need the Wavecrest SIA3000?
> >
> >On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp <lists at rtty.us> wrote:
> >
> >> Hi
> >>
> >> Since the Collins approach "tunes" the system for a single 
> >> frequency
> input
> >> (more or less), the approach is probably not the best for a "many
> decades"
> >> sort of frequency range. There are a number of things that he 
> >> alludes
> to in
> >> the paper, but does not directly address. The most obvious is the 
> >> temperature dependance of the "stuff" the system is made of. 
> >> Another is
> the
> >> simple fact that a non-clipping linear amplifier is likely the best
> choice
> >> for a first stage, provide the input is not already near clipping.
> >>
> >> Bob
> >>
> >> On Aug 21, 2012, at 12:50 PM, raj_sodhi at agilent.com wrote:
> >>
> >> > Hello everyone,
> >> >
> >> > I am new to this forum.
> >> > It looks like a lively discussion on various topics.
> >> >
> >> > A colleague of mine here at Agilent pointed me to this paper 
> >> > entitled
> >> "The Design of Low Jitter Hard Limiters" by Oliver Collins. In 
> >> Bruce Griffiths' precision time in frequency webpage, this paper is 
> >> described
> as
> >> "seminal."
> >> > (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html)
> >> >
> >> > Since I'm trying to create a limiter that will accept frequencies
> >> ranging from 1 MHz to 100 MHz, I thought it would be good to 
> >> understand
> the
> >> conclusions of this paper (if not the mathematics as well).  The 
> >> mathematics turned out to be quite challenging to decode. Has 
> >> someone on this forum unraveled the equations? It appears Collins 
> >> has
> recommendations
> >> on the bandwidth and gain of a jitter minimizing limiter, and then
> extends
> >> this analysis to provide the bandwidth and gain of a cascade of
> limiters.
> >>  But the application is still fuzzy.  In figure 5, he shows a graph
> showing
> >> the dependence of jitter on crossing time.  Is the crossing time
> (implied
> >> by equations 7) considered a design parameter one can vary? Also, 
> >> on
> figure
> >> 4, the "k" parameter has been varied to show the rising waveform as 
> >> a function of "k".  The threshold is always assumed to be 0.5.  So 
> >> could
> "k"
> >> be related to "tau", the time constant of the RC filter?
> >> >
> >> > Thanks in advance for all your help.
> >> >
> >> > Yours
> >> >
> >> > Raj
> >> >
> >> >
> >> >
> >> > _______________________________________________
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