[time-nuts] Understanding Oliver Collins Paper "Design of Low Jitter Hard Limiters"

Bob Camp lists at rtty.us
Thu Aug 23 18:07:17 EDT 2012


Hi

In general, saturated logic (TTL / CMOS) will do better than non-saturated (ECL / LVDS). Faster with saturated generally = better, provided it's silicon. Once you go to high mobility semiconductors the 1/f noise picks up. Yes, you need a quiet supply. How quiet is going to depend on your edge rates, input frequencies, phase noise offsets, the coupling circuit, and the logic used. Put another way - you need to test your circuit. There are bits and pieces of that very limited summary scattered across several hundred papers and data sheets.

Bob


On Aug 22, 2012, at 10:00 PM, Hal Murray <hmurray at megapathdsl.net> wrote:

> 
> jmulchin at cox.net said:
>> The amount of jitter verses logic family is all over the place as well. Take
>> a look at an LS verses an HCT vs an S family and you will see what I mean.
>> Some of them are very nasty, and are not all created equally.
> 
> Is there any collection of hard data?  How much does it depend upon 
> manufacturer or test setup?  How much couples through from power supply?
> 
> Does the jitter scale with prop-time?
> 
> -- 
> These are my opinions.  I hate spam.
> 
> 
> 
> 
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