[time-nuts] 32768 Hz from 10 MHz

[Tom Van Baak]

> Hi Roberto:
> 
> By changing the timer count dynamically it's possible to lower the jitter to one timer count.  See:
> http://www.prc68.com/I/PClock.shtml#BA
> 
> Have Fun,
> 
> Brooke Clarke

Hi Brooke,

You're a fellow PIC guy; let me explain.

Correct, that method works with a modest interrupt rate to count
integer seconds without long-term rounding error; but to generate
a total of 32,768 as-consistent-as-possible pulses *per* second
is quite different.

It's possible to use Bresenham with two integers 10,000,000 and
32,768 but I found no way to perform all the 24-bit calculations
on an 8-bit PIC quick enough. Removing the GCD often helps
but in this case the accumulator remains 3-bytes wide.

To generate 32 kHz you have to toggle a pin and calculate if
the next toggle must be 38 or 39 instructions in the future; all
the math must occur within 37 instructions. That's why I came
up with the binary leap year kind of algorithm; it's as close to
math-less as you can get.

By comparison, all the decimal dividers (1 Hz, 10 Hz, etc.) that
you and I do are trivial because of the common factors with the
10 MHz clock. It's just that 32,768 has no factors of 5. Read the
comments in the file 10m32k.c for more details.

I'm curious how a 10 MHz-driven high-end DDS would generate
32 kHz with the lowest possible jitter?

/tvb