[time-nuts] GPS lock of the FE5680. Current experiment and question

[David]

On Fri, 10 Feb 2012 16:35:26 -0800, Chris Albertson
<albertson.chris at gmail.com> wrote:

>On Fri, Feb 10, 2012 at 3:52 PM, Bob Camp <lists at rtty.us> wrote:
>> Hi
>>
>> I think you will need some sort of analog detector to get what you are looking for.
>
>I don't think it needs to be analog.   For example you can xor the two
>10MHz signals and then sample the digital xor output then deduce its
>duty cycle by counting how many samples are 1 and how many are 0.
>You'd expect an equal number if there is a phase lock.   Might be best
>to sample a-periodically at random.
>
>Many designs put a low pass filter on the XOR but I think random
>polling allows the software to adjust the time constant and is cheaper
>to implement.  I think you'd have the latch the xor in a flipflop as
>it would move to fast for a uP to read.

All you need for this is the flip-flop.  Clock the flip-flop with the
1 PPS signal and capture whether the oscillator is leading or lagging.
This requires the 10 MHz oscillator to be within 1 Hz but if you
divide it down before the comparison, you can extend this range as
needed to handle wider initial oscillator frequencies and larger
amounts of PPS jitter.

The simple GPSDO design in QST a couple years ago did something like
this.