[time-nuts] GPS lock of the FE5680. Current experiment and question

[Hal Murray]

paulswedb at gmail.com said:
> Why 24 bits because it was pretty easy using 74hc596 8 bit counters with
> latch and tristate outputs. Unfortunately the schematics are on paper at the
> moment scribbles. But the cntrs are stacked on top each other as a unit and
> soldered together. Only a few pins are not such as clock output enable and
> such its quite simple. The 8 bits feed a port on the micro so I can get the
> bytes. As for smaller countes indeed at this point its clear it could have
> been even 1. 

I can't quite figure out what you are planning...

Someplace, you have to consider metastability.

Since you can't read all 3 chips in the counter at the same time, you also 
have to consider the carry from one chip to the next.  I assume you are 
familiar with the classic trick of reading high, low, high, and trying again 
if the high samples are not the same.  (That's for a 2 byte counter.)

You can probably use the same ideas to avoid metastability by reading the low 
byte twice.  If you get X, X or X, X+1, you probably have a valid reading.

You still have the problem of reading both counters in sync.  I'd probably 
try something like read: high-1, mid-1, low-1, low-1, mid-1, high-1, high-2, 
mid-2, low-2, low-2, mid-2, high-2 and then try again if any of the pairs 
didn't match.  (Where "match" allows the low byte to advance by 1.)

The key idea is that the counters will be read with an offset but the offset 
will be a constant which won't cause any problems.



-- 
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