[time-nuts] Simple GPSDO

David davidwhess at gmail.com
Mon Jan 9 04:22:50 UTC 2012


On Mon, 09 Jan 2012 03:05:36 +0100, Magnus Danielson
<magnus at rubidium.dyndns.org> wrote:

>On 12/31/2011 08:15 AM, Charles P. Steinmetz wrote:
>> I know the thread began with a request for a "simple" DIY GPSDO, and
>> this may not be quite as simple as some might like. However, PPS
>> discipline is generally the simplest and most universal scheme from the
>> standpoint of interfacing to whatever GPS engine one has available. The
>> PRS10 has a clever system for PPS disclipine, using time-tagging for
>> phase detection, that mitigates the usual shortcomings of PPS discipline
>> and should be suitable for PIC/FPGA implementation.
>>
>> As implemented by SRS, the discipline parameters are more than
>> sufficiently adjustable for any need. For a homebrew version, the VCO
>> would be the quartz VCXO or Rb of your choice. The pre-filter (which is
>> selectable in the PRS10) would be a great help in dealing with the
>> jitter in a GPS PPS signal. PPS locking is discussed at pp. 14-18 of the
>> 2003 and 2005 manuals. (The manuals and Rev. H schematic are readily
>> available on the web.)
>
>The feedback is really just the PPS counter 0-9999999 modeled, and any 
>interpolation can be added without loss of generality. The time-tagging 
>is thus just sampling the state of the counter, and optionally add 
>interpolator value.
>
>You also want to have a quick-align that will reset the counter to 
>quickly jump into phase, before entering normal loop. That will save you 
>a lot of lock-in time as the phase will be in line... and worst-case 
>phase error can be half a second, so worst-case will 5 milion cycles 
>needs to be skewed, and doing that on the oscillator isn't very 
>time-efficient and causes for one hell of a initial phase error.

The design published in QST a couple years ago divided 5 MHz
oscillator by 16 to about 312 kHz and then did the phase comparison.

http://www.rt66.com/~shera/QST_GPS.pdf

>The pre-filtering exponential averager and PI-regulator is very cheap to 
>implement in a PIC, AVR or whatever. Just leave enough bits in there.
>
>I think a simple CPLD or FPGA will pull it off. You need 24 bit for 
>counting, 24 bit for time-stamp and a few more for logic. You can 
>compress the range for the time-stamp, as you only need to know "too 
>high", "too low" and a fairly small in-range value range. If you allow 
>for +/- 10 us error you only need 200 values... so there is only 8 bits.

For a simple design after frequency locking, I am leaning more toward
triggering a time to voltage converter off of the PPS output to
measure the phase and feeding that directly into a charge to voltage
integrator to adjust the oscillator.  The only digital state change is
from frequency to phase locking.

In a complex design, I would use the same time to voltage conversion
but include a calibration cycle and digitally filter in a PIC or
similar.  That would also allow direct evaluation of the PPS source.




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