[time-nuts] Controlling FEI 5680A
EWKehren at aol.com
EWKehren at aol.com
Sun Jan 15 17:58:40 EST 2012
Why do it easy when you can do it difficult. With my Lab setup the
frequency out of the Tbolt changes once in a while to correct the 1 PPS. That is
how I explain what I se on my Tracor 527E. Maybe I am wrong.
In a message dated 1/15/2012 5:12:18 P.M. Eastern Standard Time,
albertson.chris at gmail.com writes:
We are talking about a controller for the new batch of $38 FE5680
units right? Unless you modify these the frequency must be
controlled by RS232.
Then you said FPGA right? If so why worry about the bits in the
counter. You can change it later with a few minutes effort. If you
have 250,000 gates that can run at 200MHz you don't have to ration
them. Go for 24 bits and run the counter at 200MHz.
The hard part is the FE5680, I don't think anyone here really
understands it yet. How many DDS steps can you move it before it
goes out of lock. Aging and temp co. are still TBD
That is another change from a Sherra type controller, the FE5680 has a
"lock" bit. You may as well use it to disable sending frequency
One other front end change. I few people have Thunderbolts and it
would be faster to lock the FE5680 to the 10MHz signal then to the
On Sun, Jan 15, 2012 at 2:11 AM, <EWKehren at aol.com> wrote:
> I am staying out of that discussion due to lack of knowledge, My question
> is wether the input circuit is acceptable or if some one has a different
> solution. We have integrated the Shera input including the interrupt
> on the chip, so there are only three interface pins, interrupt, data
> and clock from the PIC to transfer the data. The interrupt count is pin
> selectable, just like the 5/10 MHz divide. We are presently looking at
> increasing the counter from 16 to 20 or 24 bits.
Redondo Beach, California
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