[time-nuts] Controlling FEI 5680A

Bob Camp lists at rtty.us
Mon Jan 16 09:56:26 EST 2012


The lock range of the 5680 is limited only by the range of the VCXO. The DDS has way more range than the VCXO does and there's nothing else in that loop. The rubidium cell does not change frequency when the DDS is tuned, so that entire loop is not a limiting factor. As you approach the edge of lock things will get a bit funny, that's true of any PLL. 

Based on the VCXO pictures, it's not a very fancy part. After five or more years in the field, some of them are reported to not lock at 10 MHz. Tuning one off frequency will be a try it and see sort of thing. When they left the factory they probably tuned at least +/- 3 ppm around 10 MHz and possibly ten times that. The VCXO likely has a temperature drift in the 100 to 1000 ppb range. The loop must take care of that to operate at all. 

Temperature performance per the data sheet is in the 0.1 ppb range, aging 0.01 ppb / mo (also from the data sheet). We have at least one example with a lot better aging than the data sheet would suggest. 

The only real question is weather the minimum tune range is greater than the aging for a couple years plus the variation due to temperature and other enviromental effects. The total of all of them is likely under 1 ppb and certainly under 5 ppb. The VCXO certainly will tune that far. Put another way, the tuning to put it on frequency is much smaller than the temperature drift of the VCXO. The loop is working much harder to stabilize the VCXO than it is to handle the tuning word. 


On Jan 15, 2012, at 5:11 PM, Chris Albertson wrote:

> We are talking about a controller for the new batch of $38 FE5680
> units right?   Unless you modify these the frequency must be
> controlled by RS232.
> Then you said FPGA right?    If so why worry about the bits in the
> counter.  You can change it later with a few minutes effort.   If you
> have 250,000 gates that can run at 200MHz you don't have to ration
> them.   Go for 24 bits and run the counter at 200MHz.
> The hard part is the FE5680, I don't think anyone here really
> understands it yet.   How many DDS steps can you move it before it
> goes out of lock.    Aging and temp co. are still TBD
> That is another change from a Sherra type controller, the FE5680 has a
> "lock" bit.  You may as well use it to disable sending frequency
> change commands
> One other front end change.  I few people have Thunderbolts and it
> would be faster to lock the FE5680 to the 10MHz signal then to the
> PPS.
> On Sun, Jan 15, 2012 at 2:11 AM,  <EWKehren at aol.com> wrote:
>> I am staying out of that discussion due to lack of knowledge, My question
>> is wether the input circuit is acceptable or if some one has a different
>> solution. We have integrated the Shera input including the interrupt counter
>> on  the chip, so there are only three interface pins, interrupt,  data out
>> and  clock from the PIC to transfer the data. The interrupt count is pin
>> selectable,  just like the 5/10 MHz divide. We are presently looking at
>> increasing the  counter from 16 to 20 or 24 bits.
> Chris Albertson
> Redondo Beach, California
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