[time-nuts] mixers for frequency measurement

Magnus Danielson magnus at rubidium.dyndns.org
Sun Jan 22 16:04:31 EST 2012

On 01/21/2012 06:13 PM, Ulrich Bangert wrote:
> Magnus,
>> The end result will be that the instrument limit slope hits the level of the stable source much earlier.
> Can you elaborate this claim a bit more? I Think I do not understand it in the correct way.

You have a 1/f amplitude slope from the instruments measurement limit. 
What you see when you measure is a combination of the instruments 
limitation (the slope) and the actual noise-source curve. The 
intercept-point between them depends on the instruments noise level.
Hence, the instruments measurement limit will dominate for lower taus if 
you have a quiet enough source.

>> It's more of a practical limitation of getting all those readouts that I wonder about.
> It is not "all those readouts"! The counters do the averaging inside, giving an overall measurement rate of 1/s. the external arming of 1000/s is just for keeping Tau exactly at 1s.

OK. Have you measured the dead-times? Unknown or worse, unstable 
dead-time can be a limiting aspect. Dead-time can be compensated, but it 
seems it is an art that gone out of fashion.

>> I also have another project on a FPGA ongoing with a DDMTD test, but last time I tried things I ended up with a tool problem.
> I would never claim that FPGAs are bad for time nuts projects in
> general but my own experiences (I tried things like programmable
> dividers, linear phase comparators and ps TI interval measurements)
> with FPGAs have all shown heavy problems because of unwanted
> "analogue like" interactions inside the FPGA that are difficult
> to deal with since we lack to opportunity to put a blocking C here
> ore there inside the FPGA. These effects in the sub nanosecond
> region are irrelevant for all other kind of electronics including
> VERY fast logic but the can be a disaster for time nuts.

If one beleives that the FPGA is a precision timing by itself, you are 
bound to have problems. It is a handy and programmable lump of logic and 
gates. For precision timing you need a "clean" front-end, but then let 
data-collection and high-speed dataprocessing occur in the FPGA.

For a DDMTD for instance, while the the FPGA does the full function, 
putting a pair of real DFFs up-front will clean things up and the FPGA 
side will only act as a recording device as the timing separation has 
already been done in the front-end.



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