[time-nuts] FE-5680A FAQ update: question about frequency synthesizer architecture

paul swed paulswedb at gmail.com
Fri Jan 27 14:05:30 EST 2012


Nice page really taking shape

On Fri, Jan 27, 2012 at 1:27 PM, beale <beale at bealecorner.com> wrote:

> I added a bit to the "electronics" section of the FE-5680A FAQ as below.
>
> http://www.ko4bb.com/dokuwiki/doku.php?id=precision_timing:fe5680a_faq#electronic
>
> (Note- until today, I had the 8 and 6 digits transposed, calling it the
> fe5860a. But no one noticed :-)
>
> The updated section is below. I measured the 20 MHz input and 5.3 MHz
> output of the DDS, but I'm puzzled by how the tuning resolution (4.6 mHz)
> of the DDS output is divided by such a large factor to achieve 0.18 uHz
> resolution at the final 10 MHz output. Can any frequency synthesizer gurus
> explain how this is done?
>
> -----------------------------
> The main digital electronic parts are:
>
>    Maxim DS80C323END (8051, 44TQFP, -40/+85C, 18 MHz, 4 8-bit ports,
> 64K/64K ROM/RAM )
>    STMicro PSD813F1V-20UI (1Mbit flash, 256Kbit EEPROM, 16Kbit SRAM, 3k
> PLD gates, ISP)
>    Xilinx XC9572XL VQ64BN (64-pin CPLD, 178 MHz, 72 macrocells)
>    Analog Devices AD9832BRU (25 MHz Direct Digital Synthesizer, on-chip
> 10-bit DAC)
>
> Other ICs on digital side of PCB:
>
>    Maxim MAX708 CPU supervisor
>    Maxim DS1832 CPU watchdog, brownout detect
>    Maxim MAX882 3.3V LDO (5V input)
>    Maxim MAX1246 4 ch. 12-bit ADC
>    Maxim MAX3232 RS-232 transciever
>
> Operation
>
> A 60 MHz sine from the VCXO enters CPLD pin 64 and it generates 3.3V
> square wave outputs at 30 MHz (pin 22), 20 MHz (pin 1), and 10 MHz (pin
> 49). The 20 MHz output goes to the clock input of the AD9832 DDS chip,
> which generates a 5.3 MHz sinewave output (nominal, when the RS-232 offset
> is set to 0). The frequency resolution of the DDS itself is (Fclock)/2^32
> and since Fclock=20 MHz, the 5.3 MHz output is tuned in steps of 4.657E-3
> Hz. However, the FE-5860A 10 MHz output step size is 1.7854E-7 Hz, so the
> DDS output frequency must be effectively divided in the overall system by a
> factor of about 26000 at the 10 MHz output (or a factor of 4333 at the 60
> MHz VCXO frequency). The Rb hyperfine transition is at 6.835 GHz which is
> about 683x larger than 10 MHz.
>
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