[time-nuts] FE-5680A FAQ update: question about frequency synthesizer architecture

claudio.girardi at virgilio.it claudio.girardi at virgilio.it
Fri Jan 27 18:17:58 EST 2012


Hello John,
thanks for maintaining the 5680A FAQ;
regarding its 
frequency resolution, have you checked the DDS FSELECT pin (and maybe 
also PSEL0/1) to see if they are doing some kind of "dithering" of the 
DDS frequency ?

C.

>----Original Message----
>From: beale at bealecorner.
com
>Date: Jan 27, 2012 9:01 PM
>To: "Discussion of precise time and 
frequency measurement"<time-nuts at febo.com>
>Subj: Re: [time-nuts]	FE-
5680A FAQ update: question about frequency synthesizer architecture
>
>I appreciate those notes; the data sheet for the DDS part also 
explains it. It has a 12-bit LUT driving an internal 10-bit DAC (the 
5.3 MHz sine is still a bit coarse, with < 4 samples per cycle, but in 
the 5680 it is cleaned up by an external filter).
>
>"Because phase 
information maps directly into amplitude, a ROM LUT converts the phase 
information into amplitude. To do this, the digital phase information 
is used to address a sine ROM LUT. Although the NCO contains a 32-bit 
phase accumulator, the output of the NCO is truncated to 12 bits. Using 
the full resolution of the phase accumulator is impractical and 
unnecessary because this would require a look-up table of 2^32 
entries."
>...from http://www.analog.com/static/imported-
files/data_sheets/AD9832.pdf
>
>However, my question was actually about 
how the remainder of the circuitry in the FE-5680A combines the 5.3 MHz 
from the DDS (at 4 mHz tuning step size), and the 60 MHz VCXO, to 
reference against the 6.835 GHz Rb frequency and ultimately achieve 
0.18 uHz (micro-Hz) tuning step size at the final 10 MHz output.  I 
don't think a simple multiplier-mixer-divider chain (for example) could 
give you such a small tuning step size at the output, the frequency 
ratios don't work out.  I've heard of fractional-N PLL synthesizers but 
I'm not sure if that's the principle here.
>
>>  -------Original 
Message-------
>>  From: Graham / KE9H <timenut at austin.rr.com>
>> 
>>  
The AD9832 is an Analog Devices DDS which has a 32 bit tuning word.  
>>  The way a DDS generates the output, is that it (effectively) has a 
cosine
>>  wave look-up table, with 2^32 entries that comprise a single 
cosine wave
>>  cycle.
>>  
>>  The tuning word tells it how many 
entries the DDS should advance every
>>  reference input clock cycle, 
then it pushes that amplitude value in the
>>  look-up table
>>  to the 
output D->A converter.
>>  
>>  So, if the input reference is 20 MHz, 
then the DDS can generate frequencies
>>  with a resolution step of
>>  
>>        Vref/2^32  =  20,000,000 / 4,294,967,296  =  0.0046566 
Hz.
>>  
>>  The DDS output frequency is    (tuning word /2^32) times 
Vref.
>>  
>>  In the actual implementation, rather than a 4 billion 
entry look-up table,
>>  I am sure they have some algorithm that 
calculates the amplitude of
>>  a cosine wave, or a much smaller table 
with a sophisticated interpolation
>>  routine.
>>  
>>  --- Graham / 
KE9H
>
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