[time-nuts] Zero-Crossing Detector Design?

[Azelio Boriani]

Good, I've learned also that bandwidth can matter and that a ZCD test can
done by comparison: feed the counter or TSC or TimePod or 'scope with your
source signal and 2 cables, then insert the ZCD and see the difference.
Actually I'm interested in a ZCD to feed the FPGA from the OCXO, I'm using
a 74HC04 with feedback followed by a regular 74HC04.

On Sat, Jul 21, 2012 at 4:15 AM, John Miles <jmiles at pop.net> wrote:

> > I see that from one way or the other, we always end up in a TimePod. OK,
> > then the TimePod has no comparator, no trigger but has A to D
> conversions.
> > Is the A/D conversion process supposed to be threshold-free?
>
> Hey, everybody needs at least one or two TimePods. :)  You can use a
> TimePod
> or TSC 512xA to measure additive jitter, or for that matter a mixer and a
> delay line.  But these instruments will all do the job by making a phase
> noise measurement, then integrating the plot to find the equivalent RMS
> time
> jitter.  This means that you'll have to decide what limits of integration
> you want to use.  A counter, on the other hand, will give you the total
> jitter seen across its entire front-end bandwidth, so there is less
> thinking
> involved.
>
> The trouble is, any good shaper or ZCD will have very low jitter, perhaps
> too low for even a Wavecrest-class TIC to measure.  This is what Wenzel's
> quick-and-dirty differential amp with a pair of 2N3906s looks like, when
> the
> splitter test mentioned by Bob is performed with a TimePod, TSC or other
> phase noise analyzer:
>
> http://www.wenzel.com/documents/waveform.html
> http://www.ke5fx.com/wenzel_shaper_resid_jitter.png
>
> That's about 100 fs of additive jitter, measured between 0.1 Hz and 100
> kHz.
> Because the broadband floor is relatively high, a great deal of the total
> jitter comes from the higher decades.   (The circuit's jitter contribution
> between 0.1 Hz and 100 Hz is only about 10 fs.)
>
> A counter will not be limited by the 100 kHz or 1 MHz integration range of
> a
> TimePod or TSC 5120, so you might see enough jitter to be noticeable on a
> Wavecrest in the 1 to 10-ps neighborhood.  But maybe you only care about
> jitter at lower offsets... in which case the counter will make your shaper
> look a lot worse than it really is.
>
> For instance, if the reason you're investigating ZCDs is because you want
> to
> build a DMTD, then you may be more interested in a residual ADEV plot
> instead.  The pair of bipolars contributes white and flicker PM noise, so
> its residual ADEV at t=1s isn't too different from the residual jitter in
> the ADEV measurement bandwidth, which was 500 Hz in this case:
>
> http://www.ke5fx.com/wenzel_shaper_resid_ADEV.png
>
> It's worth noting that I made these measurements on a TSC 5120A.  The phase
> noise measurement could have been made on a TimePod, but the residual ADEV
> plot could not, as it's below the TimePod's ADEV floor.
>
> To me, this says that there are better ways to spend one's time than
> designing a fancy multistage ZCD.  The important thing is to consider how
> much bandwidth is really required in your application, and whether/how it
> should be limited.
>
> -- john, KE5FX
> Miles Design LLC
>
>
>
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