[time-nuts] GPS / GNSS front-end board
Peter Monta
pmonta at gmail.com
Wed Jun 6 17:08:24 UTC 2012
Hi Attila,
> * Connect all free pins of the FPGA to a 2.54mm header pin connector
> This would make extensions to the system a lot simpler.
> Up to the point of using a simple uC board for a full fledged
> GPSDO system. Additonally put onto this connecter an unused output
> of the LMK03806 and some power supply pins.
Sure, that sounds reasonable---I'll do that. But just a caution that
it will need some work to realize a fully-fledged GPSDO, even with an
external microcontroller board. At a minimum, the FPGA would need
NCOs, code generators, correlators, and tracking loops, which people
are free to do of course.
> * The XC6SLX9 is <10USD more expensive than the SLX6. I think the added
> value of having twice as much "real estate" would justify the additional
> price.
The LX9 is pin-compatible, so substituting it in would be no problem
(actually I have a few). The current design easily fits in the LX4,
though. I guess it would be up to the user which chip to supply. I
did consider using a BGA footprint, which would allow some of the
larger FPGAs in the family, but BGAs are not very prototype-friendly.
(Nor are QFNs with exposed pad, for that matter, but there was no
alternative there.)
> * Connect the enable pin of the OSC1 to a 2-pin header, so it can be
> disabled with a simple jumper. And put a SMA connector into the path
> between OSC1 and the LMK03806 (probably not mounted by default) in order
> to make using an external clock source easier.
I was thinking to do a resistor-programmable option to either use the
10 MHz or the TCXO as input to the LMK03806. I'm not sure there's a
huge advantage to using a more stable clock, though. The TCXO is
probably plenty good enough for keeping the carrier PLLs in
lock---it's a fairly high-end TCXO which is not cheap ($18). Using
the 10 MHz (or 100 MHz) does have the merit of potentially saving the
cost of the TCXO, but many users would probably want a board that just
works, without a lot of external doodads to hook up.
> I assume that you are running the ADCs in multiplexed mode and the FPGA
> at 128MHz clock?
Yes. Actually the FPGA runs at 64 MHz and the I/O cells are used in
DDR mode so that a sample is taken on both rising and falling edge.
Cheers,
Peter
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