[time-nuts] WWVB BPSK Receiver Project?

[Attila Kinali]

On Thu, 15 Mar 2012 13:50:08 +0000
shalimr9 at gmail.com wrote:

> Poul-Henning,
> 
> Do you need 16 bits or can you get by with a 12 bit ADC?
> 
> Have you considered using an FPGA for signal processing? It seems you need a fairly serious CPU to handle that much data.
> 

I think Poul-Henning is refering to his AducLoran receiver, which
used a 1Msps ADC [1]. I dont remember what he exactly does with the signal,
but IIRC he uses a 40MHz uC which leaves him with 40 Cycles per sample,
which is quite a lot if you only do just some math calculation to detect
the start of a second...

And unlike with the FPGA, it does not take more time to process 8bit
or 24 bit samples as the uC works with 32bit numbers anyways.


			Attila Kinali


[1] http://phk.freebsd.dk/AducLoran/

-- 
The trouble with you, Shev, is you don't say anything until you've saved
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