[time-nuts] Experience with THS788 from TI?

[Ben Gamari]

Thank you very much for your response. This is amazingly helpful.

Attila Kinali <attila at kinali.ch> writes:

> On Wed, 21 Mar 2012 12:18:21 -0400
> Ben Gamari <bgamari at physics.umass.edu> wrote:
>
>> 
>> On Wed, 21 Mar 2012 09:44:14 -0500, David <davidwhess at gmail.com> wrote:
>> > I am surprised it is not more accurate and precise.  Even old discrete
>> > designs can get down to 10ps or better.  I wonder what market it is
>> > for where space is at that much of a premium.
>> > 
>> Out of curiosity, would you happen to have an example of discrete TDC
>> design? Recently I've been exploring the TDC design space as these
>> devices are a critical part of our experiments (I do spectroscopy of
>> biological molecules). I'm currently (slowly) working on a FPGA TDC
>> design (based on the PandaDAQ[1] and CERN's Spartan 6 TDC design) but it
>> seems it will be non-trivial to get down to the 12 ns the commercial
>> offerings provide (although at great cost). What would a discrete TDC
>> design look like?  Are there any designs in the open?
>
> There are multiple designs out there, some of which have been documented
> openly (in manuals, like the SR620 which is available from Didiers site)
> others are only known from papers. In general, i'd say if you need more
> documentation for a design done by a research group, you should be able
> to get help from them directly. Most people i know that work in research
> are more than happy to share their tools with others.

Really, this is more of a personal project than anything else. While I
can't say I'm quite at the time-nut level of fanaticism, I am always
looking for an interesting project where I might learn a thing or
two. If the result may one day help in a research setting, all the
better.

> If you are really going to build your own design, then i suggest you
> read these papers:

Thank you very much for this list. While I have already stumbled upon a
few of the FPGA papers, I'm largely ignorant of the other possible
approaches. Given the limitations of FPGA TDCs, it will be nice to see
what is possible by other means.

That being said, I'm quite keen on bringing up something on the FPGA. I
just got the power supplies on the PandaDAQ running last night (QFN is a
pain without my shiny new hot air rework station), so it seems that soon
enough I'll have a Spartan 6 at my disposal.

> "Time Interval Measurement Literature Review" by... uh.. dont know
> www.rrsg.ee.uct.ac.za/members/jon/activities/timcs.pdf
> Gives you an easy overview of different methods of time interval measurement
> and how they work.
>
> "Review of methods for time interval measurements with picosecond resolution"
> by Jozef Kalisz, 2003, http://ztc.wel.wat.edu.pl/kalisz/met4_1_004.pdf
> A very detailed, but broad overview of the methods that are used in todays
> TIM/TDC applications.
>
> "Time-to-digital Converters" by Stephan Henzler, 2010
> DOI: 10.1007/978-90-481-8628-0
> A more theoretic overview of TDCs. Nice if you need more math. But if
> your library doesn't have access to the books from Springer, i wouldn't buy
> it (you probably do not need all that much of math).
>
> "Error analysis and design of the Nutt time-interval digitiser with picosecond
> resoulution", by Kalisz, Pawlovski, Pelka, 1987 give you a much better
> treatment of how errors occur in TDCs and how to mathematically treat them.
>
> "An FPGA Wave Union TDC for Time-of-Flight Applications", by Jinyuan Wu, 2009
> "The 10ps Wavelet TDC: Improving FPGA TDC Resolution beyond its Cell Delay",
> by Wu and Shi, http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/WaveletTDC_abs08.pdf
> "A 20ps Resolution Wave Union FPGA TDC with On-Chip Real Time Correction",
> by Qi, Deng, Gong and Liu, 2010
> The wave union TDC is a quite interesting design that allows to get a quite
> high resolution with an FPGA only implementation. But this design depends
> highly on good placement, stable enviorment conditions (temperature, supply
> voltage) and permanent re-calibration (which in turn needs uncorrelated time
> events)

As I said earlier, I have seen these earlier. Given that the CERN core has achieved
50ps resolution without wave union, it would be interesting to see what
one could accomplish with a full wave union implementation.

> "Time-Interval Measurements Based on SAW Filter Excitation", by Petr Panek, 2007
> "Time interval measurement device based on surface acoustic wave filter
> excitation, providing 1ps precision and stability", by Panek and Prochazka, 2007
> "Random Erros in Time Interval Measurement Based on SAW Filter Excitation",
> by Petr Panek, 2008
> A very nice idea on how to use a high frequency startable oscillator with
> an ADC as phase detector. Panek claims to get below 1ps with a 200MHz clock
> and a 525MHz filter/oscillator. His calculations indicate that the ultimate
> limit of resolution is given by the sampling jitter of the ADC and the
> frequency and bandwidth (ie the Q of the oscillator). There 

This looks quite nice. I must say that I haven't 

> If you search the IEEE archvies, you will find many more examples on
> how to build a TDC. Some more, some less documented.
>
There does seem to be a number of very helpful papers around once
"-CMOS" is added to one's search terms.

> Papers by Kalisz and Pelka are always a good read. A good, and easy to
> understand example of an TDC with a Nutt interpolator is the PICTIC
> http://www.ko4bb.com/dokuwiki/doku.php?id=precision_timing:pictic
> which gives you already 680ps (RMS) with its very simple design.  I
> guess, you can get to <50ps without too much effort using a 200MHz
> oscillator and ECL devices.

Given that most high-speed comparators have dispersion of tens of
picoseconds as Tristan pointed out, this is likely as low as I'll be
able to go anyways.

> But getting to below that will not be
> easy. Mainly due to all those side effect, non-idealities and other
> stuff you have to deal with. And be aware, that you are dealing with
> an high frequncy/high speed circuit. Crudly said, you are in the
> ballpark of a 1/10ps = 100GHz system. Everything has to be right to
> get you there.

Sure. This is the real issue. I am a physicist by training, so the
basics of high-speed design are largely a mystery to me. From
application notes (in particular Jim Williams' old but very readable
work) I've gleaned the following,

1) Keep traces short and well impedence matched
2) Ample bypassing
3) Ground plane is essential

But beyond these rough guidelines my intuition isn't so well
honed. Do you have anything to add?

Given how difficult it is to even measure the behavior of a circuit at
this speed (especially given my equipment, although I could probably
find a better scope in the EE department if the need should arise), I
fully expect this will be difficult at best. That being said, it will be
interesting to try.

Moreover, this is one reason I'm first going to try getting the signal
into the FPGA as soon as possible. The less analog there is to
troubleshoot, the better.

One final question:
In Williams' notes, you often see images of point-to-point wired
circuits constructed over a copper clad board ground plane. While in the
'90s I can see this being a very reasonable approach, is it still
relevant in today's world of surface mount packages and 100GHz
bandwidths?  Assuming fly-wiring isn't an option, is there any way to
prototype a circuit capable of handling even 50ps signals short of
etching a board and hoping for the best?

Thanks again for all of your input.

Cheers,

- Ben