[time-nuts] DPLL for 10MHz

Azelio Boriani azelio.boriani at screen.it
Mon May 7 22:08:57 UTC 2012 

I'm running (although running isn't quite correct for VHDL) this on a
50Kgates Xilinx XC3S50 FPGA. Of course this can be compiled on whatever
brand of logic you prefer, I've not used any proprietary/strange (other
than local clocks, which are usually discouraged) property. Of course this
is only a piece of the whole thing but it is the starting point. I combine
4 of these to get a 2.5nS single shot resolution, driven by 4 phases of the
100MHz clock derived from the XC3S50 clock manager. The 144pin XC3S50 can
be soldered by hand, not so easy but can be done. Better get an FPGA
evaluation board.

On Mon, May 7, 2012 at 11:27 PM, Thomas S. Knutsen <la3pna at gmail.com> wrote:

> Hello.
> Thanks for publishing the VHDL code.
> What kind of device do you suggest for incorporating this? perhaps one
> that can be soldered by humans (no BGA).
> My only experience with FPGA is the Altera DE2 board we use at school.
>
> 73 de Thomas LA3PNA.
>
> 2012/5/7 Azelio Boriani <azelio.boriani at screen.it>
>
>> OK, so 1 PPS GPS to Rb -> need a TIC; 10MHz Rb to OCXO -> need a PLL. Are
>> you interested in an all digital 10nS single shot TIC that gives you a 2's
>> complement number (negative at the left of the GPS PPS and positive at the
>> right)? Here it is. This is my TIC, I use it on all my GPSDOs.
>>
>>
>> LIBRARY IEEE;
>> USE IEEE.STD_LOGIC_1164.ALL;
>> USE IEEE.STD_LOGIC_UNSIGNED.ALL;
>>
>> ENTITY PPSPSI IS
>> PORT (PPSTIEOut: OUT std_logic_vector (23 downto 0);
>> PPSInA, PPSInB, Clock100, Clock20: IN std_logic);
>> END ENTITY PPSPSI;
>>
>> ARCHITECTURE RippleCounter OF PPSPSI IS
>> SIGNAL PPSPhaseCntAB, PPSPhaseCntBA: std_logic_vector (22 downto 0);
>> SIGNAL PPSPhaseLtc: std_logic_vector (23 downto 0);
>> SIGNAL PPSADlyed, PPSBDlyed: std_logic_vector (4 downto 0);
>> SIGNAL PPSGateAB, PPSGateBA, PPSLtcA, PPSRstA, PPSLtcB, PPSRstB,
>> StopCntAB,
>> StopCntBA: std_logic;
>> SIGNAL RstGateAB, RstGateBA, OvrLtcAB, OvrLtcBA, PPSLtcA1, PPSLtcB1,
>> PPSA2BSign: std_logic;
>>
>> BEGIN
>> PPSAtoBSign: PROCESS --Sign will be 1 when A leads B (that is the TIE is
>> negative)
>> BEGIN
>> WAIT UNTIL PPSInB'EVENT AND PPSInB='1';
>> PPSA2BSign<= PPSInA;
>> END PROCESS PPSAtoBSign;
>> PPSAtoBGate: PROCESS (PPSInA, RstGateAB)
>> BEGIN
>> IF RstGateAB='1' THEN
>> PPSGateAB<= '0';
>> ELSIF PPSInA'EVENT AND PPSInA='1' THEN
>> PPSGateAB<= '1';
>> END IF;
>> END PROCESS PPSAtoBGate;
>> PPSBtoAGate: PROCESS (PPSInB, RstGateBA)
>> BEGIN
>> IF RstGateBA='1' THEN
>> PPSGateBA<= '0';
>> ELSIF PPSInB'EVENT AND PPSInB='1' THEN
>> PPSGateBA<= '1';
>> END IF;
>> END PROCESS PPSBtoAGate;
>> PPSADelay: PROCESS
>> BEGIN
>> WAIT UNTIL Clock20'EVENT AND Clock20='1';
>> PPSADlyed<= PPSADlyed (3 downto 0)&PPSInA;
>> END PROCESS PPSADelay;
>> PPSBDelay: PROCESS
>> BEGIN
>> WAIT UNTIL Clock20'EVENT AND Clock20='1';
>> PPSBDlyed<= PPSBDlyed (3 downto 0)&PPSInB;
>> END PROCESS PPSBDelay;
>> PPSPhaseErrAB0: PROCESS (Clock100, PPSRstB) --Phase error counter bit 0
>> clocked by the gated 100MHz
>> BEGIN
>> IF PPSRstB='1' THEN
>> PPSPhaseCntAB (0)<= '1';
>> ELSIF Clock100'EVENT AND Clock100='1' THEN
>> IF PPSGateAB='1' AND StopCntAB='0' THEN
>> PPSPhaseCntAB (0)<= NOT PPSPhaseCntAB (0);
>> END IF;
>> END IF;
>> END PROCESS PPSPhaseErrAB0;
>> PPSPhaseErrAB: FOR I IN 1 TO 22 GENERATE
>> PPSPhaseErrABi: PROCESS (PPSPhaseCntAB (I-1), PPSRstB) --Phase error
>> counter bit 1
>> BEGIN
>> IF PPSRstB='1' THEN
>> PPSPhaseCntAB (I)<= '1';
>> ELSIF PPSPhaseCntAB (I-1)'EVENT AND PPSPhaseCntAB (I-1)='1' THEN
>> PPSPhaseCntAB (I)<= NOT PPSPhaseCntAB (I);
>> END IF;
>> END PROCESS PPSPhaseErrABi;
>> END GENERATE PPSPhaseErrAB;
>> PPSPhaseErrBA0: PROCESS (Clock100, PPSRstA) --Phase error counter bit 0
>> clocked by the gated 100MHz
>> BEGIN
>> IF PPSRstA='1' THEN
>> PPSPhaseCntBA (0)<= '0';
>> ELSIF Clock100'EVENT AND Clock100='1' THEN
>> IF PPSGateBA='1' AND StopCntBA='0' THEN
>> PPSPhaseCntBA (0)<= NOT PPSPhaseCntBA (0);
>> END IF;
>> END IF;
>> END PROCESS PPSPhaseErrBA0;
>> PPSPhaseErrBA: FOR I IN 1 TO 22 GENERATE
>> PPSPhaseErrBAi: PROCESS (PPSPhaseCntBA (I-1), PPSRstA) --Phase error down
>> counter
>> BEGIN
>> IF PPSRstA='1' THEN
>> PPSPhaseCntBA (I)<= '0';
>> ELSIF PPSPhaseCntBA (I-1)'EVENT AND PPSPhaseCntBA (I-1)='0' THEN
>> PPSPhaseCntBA (I)<= NOT PPSPhaseCntBA (I);
>> END IF;
>> END PROCESS PPSPhaseErrBAi;
>> END GENERATE PPSPhaseErrBA;
>> StopCntAB<= '1' WHEN PPSPhaseCntAB (22 downto 1)="0000000000000000000000"
>> ELSE '0';
>> StopCntBA<= '1' WHEN PPSPhaseCntBA (22 downto 1)="1111111111111111111111"
>> ELSE '0';
>> PPSPhaseLtc<= '0'&PPSPhaseCntBA WHEN PPSLtcA='1' AND PPSA2BSign='0' AND
>> StopCntBA='0' ELSE
>> '1'&PPSPhaseCntAB WHEN PPSLtcB='1' AND PPSA2BSign='1' AND StopCntAB='0'
>> ELSE
>> PPSPhaseLtc;
>> OvrLtcAB<= StopCntAB WHEN PPSLtcB1='1' ELSE OvrLtcAB;
>> OvrLtcBA<= StopCntBA WHEN PPSLtcA1='1' ELSE OvrLtcBA;
>> RstGateAB<= '1' WHEN PPSInB='1' AND PPSBDlyed (1)='0' ELSE '0';
>> RstGateBA<= '1' WHEN PPSInA='1' AND PPSADlyed (1)='0' ELSE '0';
>> PPSLtcA<= '1' WHEN PPSADlyed="00011" ELSE '0';
>> PPSLtcA1<= '1' WHEN PPSADlyed="00001" ELSE '0'; --To be used by the
>> terminal count value
>> PPSRstA<= '1' WHEN PPSADlyed="01111" ELSE '0';
>> PPSLtcB<= '1' WHEN PPSBDlyed="00011" ELSE '0';
>> PPSLtcB1<= '1' WHEN PPSBDlyed="00001" ELSE '0'; --To be used by the
>> terminal count value
>> PPSRstB<= '1' WHEN PPSBDlyed="01111" ELSE '0';
>> PPSTIEOut<= "011111111111111111111111" WHEN OvrLtcAB='1' AND OvrLtcBA='1'
>> AND PPSPhaseLtc (23)='0' ELSE
>> "100000000000000000000000" WHEN OvrLtcAB='1' AND OvrLtcBA='1' AND
>> PPSPhaseLtc (23)='1' ELSE
>> PPSPhaseLtc;
>> END ARCHITECTURE RippleCounter;
>>
>>
>>
>> On Mon, May 7, 2012 at 7:58 PM, <EWKehren at aol.com> wrote:
>>
>> > 10 MHz between Rb and OCXO 1 pps between GPS and Rb.  Always a Rb with
>> >  GPS.
>> > Bert Kehren
>> >
>> >
>> > In a message dated 5/7/2012 1:30:57 P.M. Eastern Daylight Time,  azelio.
>> > boriani at screen.it writes:
>> >
>> > Using  the PPS as a sync source?
>> >
>> > On Mon, May 7, 2012 at 6:24 PM,  <EWKehren at aol.com> wrote:
>> >
>> > > Tried, no interest, some one has  offered to in the future do a gate
>> > array
>> > > version, you may want to wait  for that I am in the mean time using am
>> > > analog
>> > >  loop for  less than 100 seconds between Rb and OCXO and a very
>> modified
>> > > Shera  for  GPS/Rb. Works for me.
>> > > Contact me off list and we can  talk.
>> > > Bert
>> > >
>> > >
>> > >
>> > > In a message dated 5/7/2012  12:05:54 P.M. Eastern Daylight Time,
>> > > garnere at gmail.com  writes:
>> > >
>> > > This is  something I would also like to know. I'm  sure many others
>> > > would be  interested as well. Bert would it be  possible for you to
>> > > share your  thoughts on the matter with the  group at large?
>> > >
>> > > -Eric
>> > >
>> > > On Mon,  May 7,  2012 at 8:43 AM,  <EWKehren at aol.com> wrote:
>> > > > Doc   contact me off list
>> > > > Bert Kehren
>> > > >
>> > > >
>> > >  > In a message  dated 5/7/2012 11:40:04 A.M. Eastern Daylight  Time,
>> > > >  docdailey at gmail.com writes:
>> > > >
>> > > >  Does  anyone have any  knowledge of a simple (just soldering a  few
>> > > > connections and  maybe programming a hz/volt rate) PCB  for
>> > synchronizing
>> > > a  precision
>> > > > OCXO to a   GPSDO?  I am trying to improve short  term stability
>> with a
>> > >  high
>> > > > stability  OCXO and dont want to "cut  into" my  fury and replace
>> the
>> > > OCXO.  I
>> > > > cando  it  manually  but this seems like it would be nice and
>> desirable
>> > >  for
>> > > > many yet I  can't find anything.  I presume it  would have to be
>> > digital
>> > > >  because of  the long time  constant.
>> > > >
>> > > > Doc
>> > > >  KX0O
>> > >  >
>> > > > Sent from my  iPhone
>> > > >   _______________________________________________
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>> > >
>> > >
>> > >  --
>> > > --Eric
>> > > _________________________________________
>> > >  Eric  Garner
>> > >
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