[time-nuts] Adjusting HP 5065A frequency

Bob Camp lists at rtty.us
Mon Oct 22 13:53:55 EDT 2012


The gotcha with the DDS is phase truncation. That pretty much trashes the


-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Dennis Ferguson
Sent: Monday, October 22, 2012 1:44 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Adjusting HP 5065A frequency

On 22 Oct, 2012, at 12:48 , "Bob Camp" <lists at rtty.us> wrote:
> The "big bucks" approach probably is to run a good RF ADC on the input and
> then do all the offset stuff as DSP math. The VCXO just sits at it's magic
> frequency and never moves. More money / no pops. 

A somewhat cheaper way might be to use a DDS.  That is, lock
the clock driving the DDS to the input frequency and then
program the DDS to correct the measured error of the input
clock.  A DDS with a 48 bit control word will have an effective
resolution of about 4e-15, if my arithmetic is right, which
seems adequate for the purpose.

The DDS also gives you the option of generating any (corrected)
output frequency you want.  The output frequency could even be
programmable if you don't mind looking at the DDS digital noise
in the output, though that could be cleaned up by picking a fixed
output frequency ahead of time and adding a cleanup PLL for the
chosen frequency following the DDS.

I'm not sure why this problem isn't always dealt with this way,
actually.  Since the corrections are applied in digital arithmetic
the precision with which they can be made is limited only by the
bit-width of the adders you use to compute each cycle's update and,
given that the D/A converter it is driving is probably going to be
limited to 300 or 400 MSPS, even an FPGA (let alone semi-custom
logic) could carry more bits through the computation than are useful
to have.  There is probably some catch to this that I don't understand.

Dennis Ferguson

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