[time-nuts] Multiple Time Interval Counters to measure Transients?

Florian Teply usenet at teply.info
Mon Sep 10 19:45:43 UTC 2012


Hello,

Am Sat, 8 Sep 2012 21:56:45 +0200 (CEST)
schrieb Marek Peca <marek at duch.cz>:
> > Well, for the CMOS stuff 100ps should do just fine. Of course, less
> > is better, but there's only so much one can reasonably do for so
> > many channels... Even a PICTIC should be able to do better than 500
> > ps for a single channel. From what I've read, a few hundred units
> > of HP5370 should solve the problem as well, but then there's only
> > so much space...
> 
> Indeed, with such a precision, several dozens of TDCs could easily
> fit into one FPGA chip. The task is to design clever data processing
> to handle all the events.
> 
> We may be able to deliver such a custom product, but you have
> mentioned your need to save as much money as possible -- it should
> have be made more precise by means of technical specification to say
> more about time/price.
> 
Unfortunately, I don't have a more precise technical spec. I'm just
trying to find a viable solution to characterize a chip manufacturing
process with regard to Single-Event Transients. As this is supposed
to only be a side task for my PhD, I would prefer to use something that
already exists. On the other hand, until now I have no own budget, so
if I have to ask for money to buy stuff, it would better be something
that can be used for oher purposes as well.

> > I'd be very much interested. 7ps to me seems to be even more than
> > I'd need for the CMOS stuff. Just out of curiosity: Does this work
> > already from 0ps on or is the minimum count higher than that? And
> > what's the limiting factor to accuracy you experience with your
> > current design? Is it actually the FPGA and its properties or
> > something else?
> 
> Of course, the 7ps _RMS_ is the jitter of the TDC. The measurement is 
> continuous w.r.t. reference clock, i.e. "0ps" is of course possible.
> 
I was just asking because on some TDCs I read something about some 25
ps resolution and a counting range from 1 ns to 5 ms, which seems to
indicate a lower limit of 1 ns. I don't know enough about this to do
educated guesses on what this really might mean though, as I'm probably
not enough of a time-nut yet. Before, I only was interested in a
relatively stable frequency reference for amateur radio uses, so a
single GPSDO does the trick for me.

> There is (almost) no other component than the FPGA. So, the limit is 
> indeed the FPGA itself, you may include its power-supplies and 
> comparators, as well.
> 
> However, you have been probably asking, how far from the limits
> imposed bhy single FPGA cell's inherent jitter are we -- this is what
> I exactly can not answer with certainty, but according to our
> indirect measurements, best cells of the given FPGA exhibited
> estimated jitter about 1..3ps, whereas our last complete design has
> overall 7ps RMS, under the assumption of asynchronous measured
> signal. Under deterministic worst case, the precision will drop to
> 21ps abs max. (Note: this last number may be a too pesimistic value;
> stay tuned for newer revision after soldering recent pcbs).
> 
What I had in mind here was the tradeoff between the flexibility of an
FPGA and the performance of a dedicated ASIC. Of course, this very much
depends on which optimizations were done and which technology is
targeted. In most applications, a 250 nm ASIC would have a hard time
beating an up-to-date FPGA from a 28 nm process, but in some areas it
might still have its benefits. I just wondered if this might be one of
the few places where ASICs still trump FPGAs. And of course, it'll make
a huge difference if you use a low-power CMOS or a top-of-the-notch
SiGe BiCMOS...
Being at a research fab, this question came to me quite naturally ;-)

> Feel free to ask more, if you were interested in testing our device.
> 
Depends on what you refer to by "testing". I'll be definitely the wrong
guy to ask for elaborated jitter measurements, especially in the
single-digit picosecond range. But if testing means giving your stuff a
shot to see if it fits my needs, I'm all in.




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