[time-nuts] Sysclock source for AD9912

[Grant Hodgson]

Anders

You can set the overall PLL divider to any even value between 4 and 66 
as there is a fixed /2 prescaler preceding the programmable divider, so 
with a 20MHz reference (from a 10MHz source) set the overall divider to 
50 to give 1GHz - not sure if you set N to 50 or 25 in the Eval. 
software, but it's easy to do.

regards
Grant



Anders wrote :-

Thanks for all replies so far!

It looks like I will play around with the evaluation board some more, and
see if I can get the on-chip PLL to behave better.
The settings with 2x edge-detector and 60x PLL were the only ones I could
find where the output frequency setting in the software corresponded to the
actual output frequency - hence I tested only with 10MHz x120 = 1200 MHz
sysclock. I have asked about this on the AD forum, but no replies yet.

If that doesn't work the suggested ADF4351 (or similar) evaluation board
looks like the most straightforward option.

thanks,
Anders