[time-nuts] Logging the grid frequency....

Bob Camp lists at rtty.us
Sat Feb 23 02:09:12 UTC 2013


Hi

A lot depends on what the real objective is. Is the loop supposed to transfer all of the 60 Hz bumps and wiggles (wide band loop) or is it supposed to ignore them (narrow band loop) ? Given that the starting point is 60 Hz wide and narrow will be relative to that. 

Bob

On Feb 22, 2013, at 7:44 PM, David <davidwhess at gmail.com> wrote:

> On Fri, 22 Feb 2013 15:16:37 -0800, "Tom Van Baak"
> <tvb at LeapSecond.com> wrote:
> 
>>> There is a lot of noise on the line.  I'm not sure if frequency makes sense 
>>> on a cycle to cycle basis.
>> 
>> Hal, it might make sense since the OP is designing a PLL and wants to get a feel for (short-term) frequency excursions. I would guess the whole point of his experiment is to quantify this; not just say there is "a lot" or "not much" noise over some number N of cycles.
>> 
>> So that's why I posted the ADEV plot, which itself was based on timing every zero-crossing (using a time-stamping counter, not a frequency counter).
> 
> I have been thinking about this problem on and off all day and would
> probably add a sampling phase detector driven by the output of the PLL
> or just use a sampling phase detector in the PLL loop.  The sampling
> time can be adjusted independently of the PLL filtering within reason
> for whatever level of noise rejection in the measurement is desired.
> 
> That would return the phase error on every cycle or even every half
> cycle.
> 
> The whole thing of course could be implemented digitally but I like
> programming in solder.
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