[time-nuts] 10 MHz -> 16 MHz clock multiplier

[Bill Fuqua]

     One way is to divide by  10 and then multiply by 16.
Divide by 10 and then follow by 4 tuned frequency doublers.
This should introduce little phase noise.
     Another way to do it is to divide by 10, then pass the output thru a
narrow 16 MHz filter and amplify. Sounds difficult but the filter can be one
or two 16 MHz crystals followed by a simple amplifier. Look at the
reference input circuit for a PTS-160.  The output of the divide by 10 needs to
be asymmetrical so it produces even harmonics. If you are using a
divide divide by 5&2 such as a 74HC90, divide by 2 first then by 5.
  Ideally the pulse width should be a half period of 16 MHz for the maximum 
harmonic content at 16 MHz.
     You can take the output of the frequency divider and send it to a NAND 
gate.
One input of the gate is directly connected and the other is delayed. You can
use an RC with a variable capacitor to ground to get it just right.
     Just adjust the capacitor to get the maximum output from your
filter amplifier.
73
Bill wa4lav



At 07:41 PM 1/2/2013 +0000, you wrote:
>What's the simplest way to generate 16 MHz from 10 MHz? This will be for 
>clocking a microcontroller at 16 MHz given 10 MHz (Cs/Rb/GPSDO). Low price 
>and low parts count is a goal; jitter is not a concern but absolute 
>long-term phase coherence is a must.
>
>The ICS525 (as in TAPR Clock-Block) is a good candidate but I was 
>wondering if there's something cheaper, less functional, and maybe not 
>SSOP. Any suggestions?
>
>Thanks,
>/tvb