[time-nuts] (no subject)
M. Simon
msimon6808 at yahoo.com
Tue Jan 8 08:08:21 UTC 2013
To reduce cycle to cycle jitter I think a divide by 10 is in order (/5, /2). And if you can arrange it the MCU should be a little slow.
Simon
Message: 6
Date: Mon, 07 Jan 2013 18:27:54 -0800
From: Ed Breya <eb at telight.com>
To: time-nuts at febo.com
Subject: Re: [time-nuts] 10 MHz -> 16 MHz clock multiplier
Message-ID: <50EB842A.2060100 at telight.com>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Actually, I was referring to an RC and Diode network in anticipation of
the possible need for more signal shaping flexibility, depending on the
signals and circuitry. The built-in oscillators are usually self-biased
CMOS inverters intended to go with crystals, and usually a couple of
small phase shift caps to ground. If you inject the right amount of
reference frequency at the input, the oscillator should sync up. Since
it's for a fixed frequency, the required lock range can be quite small -
it needs to be enough to compensate for drift in the resonator and
circuits - so the injection level probably can be small. Since the
oscillator input has plenty of gain, and the reference is likely a very
low impedance, I think a fairly high impedance passive coupling network
to link the two should suffice, without any extra active circuitry.
Ed
Engineering is the art of making what you want from what you can get at a profit.
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