[time-nuts] How far can I push a crystal?

[Bob Camp]

HI

Different Bob, but here's the flip flop answer....


On Jan 18, 2013, at 5:11 PM, Ed Breya <eb at telight.com> wrote:

> Bob, please tell me more about cascading the DFFs. I was only using one half of the '74, with the other inactive, so both are available for the task. From your description it sounds like I just run the Q from the first DFF to the D of the second, clock them together from the 1 or 10 MHz, and take the cleaned up difference signal from the Q of the second. So, I think what it means is that the same information should pass through, just delayed by one sampling clock cycle, and scrubbed of any edge uncertainty of an analog nature, that would otherwise be passed to the phase detector. Right? I would definitely do this if no additional logic packages are required.
> 

The gotcha with any flip flop is that it can get confused if you hit it just wrong. Exactly what constitutes wrong varies a bit depending on what kind of flip flop it is. In the case of a D flip flop with an edge sensitive clock, wrong is the data and clock changing at just about the same time. There is a possibility that the flip flop goes into oscillation rather than latching to either a 1 or a 0 state. If there's enough gain, it can keep on going until the next clock edge comes along. Obviously, this isn't what you want it to do. By cascading flip flops, you have much less chance of things hitting the final flip flop and creating an oscillator. 

Bob


> If a single-PLL type we discussed earlier is workable, I won't even need to worry about the second PLL system. It all depends on whether the phase detector frequency will be high enough. I'll be thinking through that and trying a few experiments. It's simple enough that I could even just build it and see what happens. If it's not right, then I'll just go with the previous plan, with high confidence - and a two-stage sampler.
> 
> Regarding the oscillators - yes, having different signals present in common packages is what got me into this trouble in the first place. As I mentioned earlier, I had optimized the original design for compactness and minimum package count, so I had every signal in the box going every which way, all mixed up. I had used a different method for making the 10.7 MHz though - building it up by mixing various divided frequencies, then filtering it with cascaded 10.7 MHz IF filters. Most of the stuff went right around the filters anyway, since there was so much whizzing around in there.
> 
> In case anyone is wondering why I'm so hung up on this 10.7 MHz thing: For this particular tracking generator project, I just need to synthesize one fixed, "correct" reference frequency with the simplest, most compact scheme that performs well enough. The original design evolved from using the 10.7 MHz base frequency, but it isn't actually needed per se. If anyone comes up with sets of numbers that seem to work in a single-PLL scheme, and fit the constraints evident in this discussion, please let me know.
> 
> I have other tracking generator projects in the works though, that will cover most or all of the 8566B span of ~0 to 24 GHz, and need to produce various numeric and harmonic relationships for IFs and frequency control - all of these can be readily integer-derived from the fundamental 10 and 10.7 MHz references. In all cases, the ultimate reference is the 10 MHz used or produced by the 8566B, so everything is phase locked.
> 
> Ed
> 
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