[time-nuts] Is there any way to use a TIC to measure time of reflection on a PCB?

[Magnus Danielson]

On 01/23/2013 07:03 PM, David Kirkby wrote:
> On 23 January 2013 15:22, Jim Lux<jimlux at earthlink.net>  wrote:
>> On 1/23/13 6:48 AM, David Kirkby wrote:>>
>>> A student needs to find the open-circuit fringing capacitance of a
>>> piece of microstrip line. For this he needs to know the time between
>>> the reference plane of the SMA connector and the open circuit
>>> microstrip.
>>
>>
>> Can he build multiple microstrips with known distances, and measure them all
>> and solve for it that way?
>
> I'm not sure how that would help. The basic problem is that there is
> some discontinuity of impedance between the microstrip and SMA
> connector. The open reflects 99% of the incident power, and that
> discontinuity then causes the power to go back to the open. So it
> seems to me one needs some form of time-gating. Also there's the issue
> of how reproducible it would be to solder SMA connectors to a board.
>
>>> An obvious way to do this is with a vector network analyzer with a
>>> time-domain option. In HP/Agilent VNAs, this is option 010. The
>>> student has access to an obsolete and unsuported HP 8753C 6 GHz VNA,
>>> but it does not have the time-domain option.
>>
>>
>> Does it have the "measurement plane offset" option?
>
> Yes - it is called "port extensions" in HP language.
>> I'm not in front of my
>> old analyzer in the lab (8720C.. no disk drive), and it does have the
>> transform option, but I'm not sure you need that option to have the "dial
>> an offset" in the calibration.  I've used that to move the reference plane
>> from the connectors at the edge of a board to the device on the board:
>> testing a vector modulator with the display in polar coordinate mode, for
>> instance.. you keep turning the knob til the display is a dot, not a circle
>
> That is not really the right way to do it, since there will be some
> fringing capacitance. You have not removed that - just appeared to
> have done, but have faked that by setting the offset delay. You have
> chosen an offset delay of less than the true value.
>
> But to a first degree, delay in the transmission line and delay caused
> by the capacitance are similar. See: "
>
>
>
>> What measurement uncertainty is called for here?
>
> It's an undergraduate project. I don't suppose he has been given such data.
>
>> Can you make your own
>> limited purpose cal kit? The open is the challenge.  Shorts, loads, and
>> thrus are fairly straightforward.
>
> The idea of his project is to characterise devices - I'm guessing
> surface mount. For this he needs a calibrated microstrip line. So the
> whole point is to characterise this.
>
> As you say, the open is the challenge. Knowing what the length to the
> open is, you an dial that into a VNA as a port extension, then read
> off the capacitance of the open since you have moved the reference
> plane to there. However, if you chose a different value of port
> extension, you will read a different value of capacitance.
>
> Also the fringing capacitance is frequency dependant - it is not a
> constant, though it is quite close to being a constant. I believe he
> has arrived at a offset length, but it has been pointed out he had
> done this the wrong way. One really needs the TDR option. The
> procedure would be:
>
> * Use the TDR, which is basically an inverse Fourier Transform.
> * Put a gate around the reflection from the open.
> * Transform the data in the gate back the the frequency domain. This
> allows one to look at the frequency domain response of the open,
> whilst ignoring that due to other discontinuity.
>
> But of course to do this one needs sufficient discrimination in time,
> to look at just the open, and not anything else. His VNA does not have
> the frequency response to do that, even if he gets the TDR option.
>
> He has arrived at an offset delay, using a method similar to what you
> described. But it has pointed out to him that the idea is not to make
> the open look a spot, but to determine what the capacitance is. In
> that case, the open does not look like a spot.
>
> In fact, on my 3.5 mm kit, the open actually becomes a short at one
> frequency, but then the short has become an open. I see about 200
> degree of phase shift of both the open and short over the range 50 MHz
> to 9 GHz. It does not matter, as long as the phase of the open and
> short remain around 180 degrees apart.
>
> Once he arrived at an offset, he moved the reference plane there, then
> measured the capacitance as a function of frequency. He then fitted
> that to the equation of the form
>
> C = C0 10^-15 + C1 10^-27 f + C2 10^-26 f^2 + C3 10^-45 f^3.
>
> Once he tried to enter C0, C1, C2 and C3 into the VNA, as a
> user-defined calibration kit, he was unable to do this, as the
> constants are too large.
>
> I think he has got the offset wrong, so he has moved the reference
> plane to the wrong place, so the constants are incorrect and unusable.
>
>> Maybe you have to collect the uncalibrated
>> data with the cal standards and do the "cal" in post processing in Matlab or
>> something.
>
> I think his basic issue is that the time domain discrimination is too
> large. I rather suspect an Agilent employee might have given him the
> code to enable the TDR, but Joel Dunsmore has determined the TDR would
> be no use to him, due to the 6 GHz upper limit on his VNA.
>
> Joel has said he needs a time resolution of about 100 ps, which means
> using a 20 GHz VNA. This got me wondering if there was any way a
> time-interval counter could be used instead of the VNA to find the
> offset to the open.
>
> I think his best option might be to make the PCB longer, so the delay
> is sufficient to making time-gating practical. Then I expect some kind
> sole from Agilent might give him the code to enable the TDR option.
>
> Another option he has, which I think might be his best one, is to
> assume a fringing capacitance of 50 fF. He has been told it will very
> close to 50 fF. If the port extension was then close to show a
> capacitance of 50 fF, he knows what the offset delay of the open is.
> Then using this cal kit, he would set:
>
> C0=50, C1=C2=C3=0.
>
> Since he originally got a C0 of about 100 fF, I think he is well out
> on the offset delay.
>
> I think given the limitation of his equipment, that might be the best
> he can do. But if a time-interval counter could do better, it would be
> worth trying.
>
> I must admit I can't see how a TIC could help, but I thought I'd ask.

It will be very hard for a TIC to help you, you need pretty good pulser, 
delay generator and level measurement, and that's about all that builds 
up a TDR. Essentially a high speed sampling scope and a good pulser 
would do it, but good enough pulser might be where you fail.

I have not been satisfied with the resolution of the TDR option on VNAs 
compared to real TDRs like the one I have. Also, the assumption of 
cyclic signal of DFT isn't really applicable to the real world situation.

I would strongly suggest that he finds himself a TDR. I would offer to 
measure it if I was sure I had a quick path to dumping the data, which I 
currently do not have.

Cheers,
Magnus