[time-nuts] Clock Driver Design

[Magnus Danielson]

Hi Bob,

On 09/27/2013 01:44 PM, Bob Camp wrote:
> Hi
>
>
>
> Rise and fall times are not the thing to worry about on the gates. Look at the propagation delay. That's what will vary. 
>
>
> On Sep 27, 2013, at 2:11 AM, Tom Minnis <Tom_minnis at att.net> wrote:
>
>> Thanks for all your thoughts on the subject.  Let me play back what I have learned and how it may apply to my challenge.  One of my first applications is to use a 10MHz output to phaselock a VCXO master clock in a radio transceiver.  The VCXO is the Christek CVHD-950 which has a noise floor of -164dBc and is -86dBc at 10Hz.  The source I want to use is the Jackson Labs GPSTCXO which has a noise floor of -155dBc and is -73dBc at 1Hz and 103dBc at 10Hz.  i did a quick survey of the phase noise specs on various Jackson products that claim to be ultra low phase noise and found similar numbers.  One was -100dBc at 1Hz but only -145dBc at 100KHz.  Another was down -90dBc at 1Hz and -160dBc at 100KHz.  It would appear that even the best parts I could find quickly would not merit the fancy analog gizmo and that a good stiff logic buffer would work.  Next I went to IDT to find the best logic buffer I could find.
> The phase noise out of a TBolt is roughly -165 to -170 floor and -155 to -160 at 100 Hz. (plus spurs of course)
>
>>  I am looking at the IDT 74FCT38072 2 channel clock driver for PPS.  It can drive about 50mA if needed with 1nS rise and fall times.  The one I am looking at for 10MHz is the ICS553 4 channel clock driver.  This one is good for 25mA drive and they actually give a typical output impedance spec of 20 Ohms.  With a 3.3V supply, it has 1nS rise and fall times and a little faster with a 5V supply, 0.7nS and 35mA drive.  
> Rise and fall times are not the thing to worry about on the gates. Look at the propagation delay. That's what will vary. If a 3 ns delay varies 1% (30 ps) over 1,000 seconds that's going to give you 3x10^-14 in your ADEV. Are your sources good to 3x10^-14 at 1,000 seconds? If not, don't worry about it. 
Indeed. I would assume that temperature and power supply voltage be the
major contributors, and both can be handled if you care about it.
>> To make a sine wave should I use one of the 4 ports on the 4 port driver to input to the filter or should I try to hook the filter input directly to the clock driver input?
>> Are there tried and true 10MHz filter circuits or is that a non issue?  After the filter would come the video amp set up for a 50 Ohm drive and into a splitter.  That sound simple enough.  What am I missing?
> Simply use a three element Tee on the output of a logic gate. Run one per output. Don't split for multiple output. That way you will have much better isolation (which very much does matter). 
Isolation is indeed something to care about. Just consider the effect of
someone connecting or disconnecting a cable. The unconnected output will
see the energy bounce back while the connected (and destination loaded)
output will transmit energy out. As you swap between these, the
isolation steers how well that is hidden from the other outputs. In a
precision environment, bad isolation essentially means you can't touch
it when it is operating. With isolation you can connect and unconnect
more freely even if the other outputs is operational.

A customer once asked if they could passively divide a signal (which is
wide-band) using a BNC-T. For the production environment they where
going to install, I more or less forbid them to do that. They where
thinking MTBF and cheap solution, but the lack of isolation means that
*any* fault will potentially kill both legs and there would be no
maintenance possible. Their counter-argument was that "well, if you cut
the cables to the wavelength" and I then pointed out that it only works
for sine and narrow-band signals, but this wide-band signal will not
handle it well. They took my advice to the best of my knowledge.

Cheers,
Magnus