[time-nuts] First success with very simple, very low cost GPSDO, under $8
Hal Murray
hmurray at megapathdsl.net
Thu Apr 10 04:07:44 EDT 2014
> But I still need to count all the cycles in the second and can't just let a
> 8 or 16 bit counter run free. The reason is I don't know where the
> overflow happens. Overflow is not in sync with PPS.
> OK this might work. I hope it does as it would allow a bit of code to be
> removed. Let's see...
> The system powers up, I enable the 8-bit counter and then assign an
> interrupt handler to the PPS and enable the PPS interrupt and I get the very
> first PPS interrupt and notice the counter vale is 67.
> At the next interrupt the counter is 82
> With only these two numbers 67 and 82 and knowing the counter is 8 bits how
> to I know the "error" which is the number of cycles different from 5000000.
> Or more simply: "after reading the 82 how to I adjust the DAC?"
> If you can spell it out I'll try it. But I bet you need one more number:
> the count of the times the 8-bit counter overflowed.
> OK we might be able to assume a number of overflows because there are tight
> bounds on the PPS and OCXO performance.
...
I think it will be obvious after you see it. The basic idea is to do
everything mod 256.
I think your current scheme is roughly:
read the counter (including overflows)
subtract the previous counter
subtract 5000000 (0x4C4B40)
the answer should be -1, 0, or +1
If things are way off, it might be 4 or 5 bits plus a sign bit.
To do that with just an 8 bit counter, subtract the bottom 8 bits of 5000000
There might be X or X+1 overflows in the main counter. There can also be an
overflow when you subtract the previous counter and/or when you subtract
5000000. I think the total number of overflows will be the same each second.
How big is your counter plus overflows? 24 bits? (that covers 5000000) 32
bits? Eventually, the "read the counter (including overflows)" step is going
to overflow. But then there will be an overflow when you do the subtract the
previous counter step.
--
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