[time-nuts] 74HCT9046A Max. Operating Frequency

[Magnus Danielson]

Alex,

You should direct your comments to Samuel that is doing a design.

I know very well about keeping the comparator frequency high, and that 
the 9045 may not be the ideal comparator.

Cheers,
Magnus

On 04/30/2014 02:53 AM, Alexander Pummer wrote:
> Hi Magnus
> if you do not need to use the VCO  of the 74CHXX46, just the phase
> detector you could find better device at Analog Devices like the AD9901
> and many others and you could use higher comparation frequency to, here
> is how to do it:
> http://www.microwavejournal.com/articles/21968-synthesizers-looking-beyond-the-basics
> with higher comparation frequency you will have less headache because of
> the spurious in the VCO spectrum
>
> 73
> Alex
>> Alex,
>>
>> Sure, but is that close-in phase-noise or wideband white noise?
>> It matters greatly how it is distributed in frequency.
>>
>> Most importantly, is it low enough to recover the clock.
>>
>> If it is too high, then one needs to use another VCO.
>>
>> In this case, he only wanted to use the 74HCT9046 as a phase
>> comparator and then steer a VCXO, so the 9046s VCO phasenoise would
>> not be relevant.
>>
>> The clock recovery PLL only have to have decent phase noise above 8
>> kHz, as below that it is being suppressed by the loop and replaced by
>> the source (and lower frequency systematics from cabling and ISI).
>> Sure, near 8 kHz it needs to be decent as the suppression isn't perfect.
>>
>> Then comes the much narrower PLL.
>>
>> Cheers,
>> Magnus
>>
>>
>> On 04/29/2014 02:21 AM, Alexander Pummer wrote:
>>> the CMOS chip: PLL 74HC4046, 7046, 9046, will have substantial phase
>>> noise, particularly close to the higher end of the usable frequency
>>> range..
>>> 73
>>> Alex
>>>
>>> On 4/28/2014 1:30 PM, Magnus Danielson wrote:
>>>> Chris,
>>>>
>>>> On 04/28/2014 04:16 PM, Chris Albertson wrote:
>>>>> On Sun, Apr 27, 2014 at 11:41 PM, sg sg <micpreamp at yahoo.de> wrote:
>>>>>
>>>>>> Thanks very much for your responses!
>>>>>> ..
>>>>>> The source is an AK4114 AES/EBU audio receiver, which has both master
>>>>>> clock (24.576 MHz) and "word select" rate (48-192 kHz) outputs.
>>>>>> Perhaps it
>>>>>> is better to run the PLL at the latter? Any disadvantages from this?
>>>>>
>>>>>
>>>>> So this is for clock distribution in a studio?   While our eras don't
>>>>> care
>>>>> about nano seconds or even micro seconds we do care that long of the
>>>>> same
>>>>> length have exactly the same number of samples.  In other words at a
>>>>> given
>>>>> times into a track, all tracks have the same number of samples.    I
>>>>> think
>>>>> what matters in this application is long term stability over days,
>>>>> weeks
>>>>> and even years.   So the first step is always to figure out your
>>>>> requirements and USE NUMBERS.
>>>>>
>>>>> Next.  It is not "either/or"  you can put the PPL at 24..5MHz or 48K
>>>>> or you
>>>>> can divide by 10 and put the PPL at 2.45Mhz.  or any place in between.
>>>>>
>>>>> One question:  Why use the receiver as a clock source?  Most use
>>>>> something
>>>>> independent like an OX or even Rb then use that to drive a DDS chip.
>>>>>
>>>>
>>>> Rb is way overkill. Beyond keeping things in sync to ensure same
>>>> sample rate, what is important is jitter but not ppm level wander.
>>>> Jitter can kill your listening experience by to ways, one is bit error
>>>> rate, causing bits to be incorrect. The second is that it creates
>>>> side-bands, which causes issues when you try to achieve 24 bit
>>>> resolution, or for that matter 130 dB dynamics. Do read what Julian
>>>> Dunn had to discuss on that matter, since he look at what sidebands
>>>> would do, considering masking effects of psycho-acoustics etc.
>>>>
>>>> Then again, we being time-nuts, overkill is easy to achieve.
>>>> We need to be careful about jitter as we re-synthesize and lock things
>>>> up. Jitter-peaking as a cause of jitter accumulation, and that leads
>>>> to... bit errors and side-bands.
>>>>
>>>> Cheers,
>>>> Magnus
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