[time-nuts] Ublox neo-7M GPS

Hal Murray hmurray at megapathdsl.net
Thu Aug 21 16:16:21 EDT 2014

tnuts at toneh.demon.co.uk said:
>> Tony, any chance you could do a quick measurement at 8 MHz -
>> I think that should be a more constant period.  ... 
> No problem, its still set-up. As you'd expect its rock solid at 8MHz  with
> no visible jitter. 

I don't think you have fixed the problem, just made it harder to see.

Do you have a digital scope?  If so, set it up with the infinite persistence 
mode, scroll the time delay out a long time, and wait a while.  I'll bet you 
get one that is shifted by a cycle before long.  If you wait long enough, you 
will see the short/long half-cycle on the scope.

If I understand what's going on, it's a classic DDS.  The basic idea is that 
you have a wide adder.  Think of the binary point as being on the left.  Each 
clock cycle you add a magic number.  For a sine output, you take the top N 
bits of the adder, run them through a lookup table (ROM) and into a D/A 
converter.  For a square wave output, just use the top bit.

If you are adding 0.001 (binary) the top bit will toggle every 4 cycles.  
That's dividing by 8.  If you add 0.001000000001, then occasionally you will 
only get 3 cycles between transitions.  If you add 0.00011111111111111, then 
occasionally you will get 5 cycles.

If you add 0.001001, then occasional changed to frequently and you can easily 
see it on a scope.

There are a handful of interesting properties:

  Except for a few magic target frequencies, the output will have occasional (or frequent) missing or extra cycles.  The output will be clean if you are dividing by a power of 2.  (By switching from 10 MHz to 8 MHz, you have changed from frequent to occasional.)

  You can only get some output frequencies.  For example, you can't divide by exactly 10.  In binary, that turns into a repeating fraction.[1]  With a wide enough adder, you can get very very close.

  If you pick a frequency that you can get, the long term ADEV output will be as good as your system clock.  If your target is some other frequency, it will drift, but the long term drift will be as solid as your clock.

  In the time domain, those extra/missing cycles turn into spurs.  If you take the magic number and throw away all the 0s on the left and right, the width of the remaining number tells you how close in the spurs will be.


1] With a FPGA, you could build a decimal adder rather than a binary one.  That would allow a clean divide by powers of 10.

If you are only interested in the clean cases, you could build a divide by N.  It's just a down ounter that reloads to N on overflow.  If N is odd, the output will not be 50-50 duty cycle.

These are my opinions.  I hate spam.

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