[time-nuts] TIC model

Lars Walenius lars.walenius at hotmail.com
Sat Feb 15 18:13:40 EST 2014

>>Bob Stewart wrote:
>> Tom tried to steer me to the PICTIC recently, and I sort of brushed him off, because, quite frankly I didn't understand.  Now that I've really looked at it, it's a much better idea than using a dsPIC33 and brute-forcing it.  But, I don't really need everything the PICTIC offers so I started doing surgery, and this is what I've come up with. 
>> The nsVolts would feed one of the 10-bit ADC channels of the 18F2220 on the VE2ZAZ board, and the 1PPS signal does the obvious.  I had no idea what to use for the RC, so I used smaller and smaller values till LTSpiceIV showed a large range over 360 degrees of phase.  I realize that's probably a bad idea, but I have no point of reference, nor do I probably need the accuracy that would otherwise imply. 
>> The 1PPS input passes through the enabled tri-state buffers U2A and U2C to charge the cap until the Q output from the D-flop is sent high from the 10MHz signal and disables U2C.  When the 1PPS goes low, the cap is discharged and the D-FLop is reset.  In practice, the chips would be 74AC types.  I could only find LTSpiceIV models for 74HCT chips.  LTSpice says it's workable, but in practice, I don't know.  It might be finicky or unstable.  Any comments would be welcome.
>> http://www.evoria.net/AE6RV/TIC/TIC.png
>> Bob - AE6RV

>  Bruce Griffiths wrote:  
>You should also include the effect of the A/D converter sampling 
capacitance and saampling switch series resistace in the model. Since 
the RC time constant of the sampling switch and associated sampling 
capacitor can be 1us or more (temparature and Vcc dependent) the voltage 
waveform at the sampling capacitor differs significantly from that 
predicted by your simple modeel.
Aside from the nonlinearity due to the non constant charging current the 
principle limitation on the resolution is due to the variable interrupt 
latency for ADCs where the conversion is triggered by software.
This problem can be avoided if the ADC conversion can be triggered 
directly by an external signal.

What Bruce says is really important.

For the ATmega328 the datasheet says 14pF sampling capacitance and nothing about temperature coefficient.

It also specifies a series resistance 1..100k. So not very precise. If it is 100k the time constant is 1400ns!

I have tested several boards and they seem to behave similar with my 1nF NPO capacitor. With a 47pF I guess it is more uncertain.

I also recommend you to test your model in the real world. I have used two good OCXOs and/or rubidiums with a small offset. Say 1E-9 offset that gives 1nS per sec. One of the channels have had a divider for example HC390s or the excellent PICDIVs from Tom Van Baak to output 1PPS.

I have also applied a heat gun near the circuit to test that the circuit doesn´t drift with temperature. A reasonable goal is to have less than 1LSB drift with a couple of degrees change. This test I have done with the same source for both 10MHz and 1PPS and a high reading from the ADC.

What Bruce says about interrupts is also worth to check in real life as “jitter” due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS.

time-nuts mailing list -- time-nuts at febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

More information about the time-nuts mailing list